Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs

• US 5,202,889 A
• Filed: 11/13/1990
• Issued: 04/13/1993
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shwartzburd, Victor, Leibowitz, Moshe, Gofman, Emanuel, Gewirtzman, Raanan, Bar-David, Ayal, Aharon, Aharon
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US07/612,349
• Time in Patent Office: 882 Days
• Field of Search: 371/27, 371/20.4, 371/21.3, 371/24, 371/5.2, 371/22.3, 371/25.1, 364/488, 364/578
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern

Abstract

In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.

Claims

1. Dynamic process for generating biased pseudo-random test patterns for the functional verification of an integrated circuit design, wherein the verification is performed in a sequence of steps defined by a user, and wherein each of the test patterns provides all data required to test the circuit design during at least one of said steps, said process comprising:

a) performing each of said steps in a first and a second stage, wherein facilities and parameters required for executing said step are defined and initialized in said first stage, and wherein said step is executed in said second stage;

b) repeating a) until the test pattern having the number of steps requested by the user is generated, and whereupon completion of said generation said test pattern comprises;

the initialized facilities that define an initial machine state;

the execution of the step that drives the simulation of said design; and

final values of said facilities that incorporate changes that occurred during the execution of said steps to include expected results of said test pattern.

2. The process in accordance with claim 1, further comprising storing for later retrieval intermediate states of said facilities after executing each of said steps.

3. Process in accordance with claim 1 wherein the initialization of one of the facility in said first stage is performed if, and only if, the respective facility has not been set yet, and if it is used as a source in the currently generated step, or if it influences in any way the execution of the currently generated step.

4. Process in accordance with claim 1, wherein the execution of said patterns may occur in an arbitrary order.

5. Process in accordance with claim 1, wherein an assignment of values to said facilities is performed in accordance with biasing strategies defined by the user or selected randomly, said strategy is selected from a group that consists of:

creating a specific sequence of instructions and selecting an instruction having a source operand, wherein said operand is a destination of a previous instruction.

6. Process in accordance with claim 5, wherein an initial set of said biasing strategies defined by the user is evaluated during coverage analysis of the test patterns generated thus far, said coverage analysis comparing a reference model of the design to an actual design model.

7. Process in accordance with claim 1, wherein every circuit comprising the design is tested at least once.

8. Process in accordance with claim 5, wherein within said biasing strategies, data is generated pseudo-randomly and control parameters of the process are stored so as to permit later regeneration of the generated test patterns.

9. Process in accordance with claim 1, wherein during execution of said step in said second stage, a reference model of the design is used, the model being incorporated as part of the process.

10. Process in accordance with claim 5, wherein the quality of the test patterns under generation is monitored by coverage analysis, said coverage analysis is being performed in accordance with testing techniques that include covering of branches and paths in a reference or design model, and wherein feedback from said coverage analysis is used for improving the biasing strategies and for evaluating the efficiency of said functional verification.

11. Process in accordance with claim 10, wherein said coverage analysis is initially performed on a reference model with the test patterns generated used as a starting set for the design verification, said verification process is subsequently followed by the coverage analysis being performed on the design model, wherein the patterns created are used as a basic set for regression testing.

12. Process in accordance with claim 5, wherein the initialization step comprises:

feeding basic parameters which control said first stage;

defining and setting the facilities involved by selecting said biasing strategy, setting the contents of a machine state register and defining the memory limits;

generating a current instruction address;

checking the addressed memory location for a completed definition and, if so, indicating that it is "free," and if not, fetching an instruction from storage;

initiating the generation of an instruction by selecting an opcode from an opcode list and building an instruction word consisting of fields by using a field list or by using said biasing strategy;

assigning to all operands their respective values based on said biasing strategy, and wherein

said execution step comprises;

executing the accessed instruction taking into account that all involved facilities have been set in the first stage,

updating all affected facilities and their marking containing a test pattern result,

determining whether sufficient steps have been generated as required by controls of the process, and

if so, having obtained results compared with expected results, wherein after a generated test pattern is written out, and

if not, the test pattern generation process is repeated until a required number of steps are obtained.