Block error detector

• US 5,202,890 A
• Filed: 06/07/1990
• Issued: 04/13/1993
• Est. Priority Date: 06/09/1989
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Co. (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mizuki, Hiromasa, Iketani, Akira
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/534,276
• Time in Patent Office: 1,041 Days
• Field of Search: 371/57.1, 371/37.4, 371/40.3, 371/31, 360/38.1, 360/49, 360/53
• US Class Current: 714/765
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: H04N 5/945 for signals recorded by pulse code modulation

Abstract

A train of data blocks, each carrying digital data and ID data are produced from a reading head as a tape passes the cylinder. A memory having a plurality of sections is provided, and a plurality of counters are provided correspondingly to the sections. The digital data are stored in a memory section identified by the ID data. Each time the digital data for one block is stored in a section in the memory, a counter corresponding to that section is incremented, and each time the digital data for one block is read out from a section in the memory, a counter corresponding to that section is decremented. Thus, as long as counter repeats "0" and "1", the data block is properly stored and properly read. However, if any one of the counters shows a number other than "0" and "1", it is understood that the writing or reading has been carried out twice in a row for the same section in the memory. Thus, an error in the ID data can be detected.

Claims

1. A block error detector for detecting an error in data blocks, each block including sub-blocks consisting of an ID block and an information block carrying a plurality of information signals, said block error detector comprising:

a memory means having a plurality of sections, each section having a plurality of segments for storing information signals for a plurality of data blocks;

a writing address generator means for generating a section writing address based on said ID block for designating a section in said memory means, and for generating a segment writing address for designating a segment in the designated section;

a plurality of counters provided correspondingly to said plurality of sections, respectively, and operated in response to said section writing address; and

a detector means for receiving counted results of said counters;

wherein said detector means includes a means for detecting an error in said ID block when all of said plurality of counters, which are incremented by "1" when all the ID data has been properly detected, have not been incremented by "1".

2. A block error detector as claimed in claim 1, further comprising:

a reading address generator means for generating a section reading address at a predetermined frequency for designating a section in said memory means, and for generating a segment reading address for designating a segment in the designated section; and

a switching means for switching between a writing mode in which the block data is written into said memory means by the control of said writing address generator means, and a reading mode in which the block data is read out from said memory means by the control of said reading address generator means, said switching means further switching said counters into a first mode of operation during said writing mode and a second mode of operation during said reading mode operation.

3. A block error detector as claimed in claim 2, wherein said counters are in a count up mode during said first mode operation, and are in a count down mode during said second mode operation.

4. A block error detector as claimed in claim 2, wherein said counters are in count up mode during said first mode of operation, and are in a shift mode for shifting the contents of a counter to said detector means during said second mode of operation.

5. A block error detector as claimed in claim 1, further comprising a data converter which receives a signal indicating an error from said detector means for correcting data error in data blocks.

6. A block error detector as claimed in claim 5, wherein said data converter is disposed in a line for sending information data read out from said memory means.

7. A block error detector as claimed in claim 5, wherein said data converter is disposed in a line for sending information data into said memory means.