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Digital discriminator for pulse shaped .pi./4 shifted differentially encoded quadrature phase shift keying

  • US 5,202,901 A
  • Filed: 05/21/1991
  • Issued: 04/13/1993
  • Est. Priority Date: 05/21/1991
  • Status: Expired due to Term
First Claim
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1. In a receiver of a cellular telephone for receiving phase angles encoded in a received signal, a digital discriminator, said discriminator comprising:

  • a) a heterodyne circuit for converting said received signal to an intermediate frequency (IF) signal;

    b) an analog to digital (A/D) converter circuit coupled to the heterodyne circuit for sampling said IF signal and for creating a digital output signal having a plurality of samples, each sample comprising a quadrature coefficient signal and an in-phase coefficient signal;

    c) a sorter circuit coupled to receive the digital signal from the A/D converter and provide a predetermined number of samples for decoding;

    d) means for producing an initial sample index;

    e) a sample and phase adjustment (SPA) circuit coupled to the sorter circuit for receiving the samples of the sorter circuit, coupled to the means for producing an initial sample index for receiving an initial sample timing index, for receiving a sample timing index, for selecting samples for decoding based upon the sample timing index, for receiving a carrier phase adjustment, and creating a set of output samples based upon the selected samples and carrier phase adjustment, each SPA output sample comprising a quadrature coefficient and an in-phase coefficient;

    f) a means for providing a set of relative phase angle samples from the set of output samples from the SPA circuit, the relative phase angle providing means coupled to the SPA circuit;

    g) a modulo-2π

    correction circuit coupled to the relative phase angle providing means for receiving the relative phase angle samples, for correcting for phase angles which wrap-around the real axis and for creating a set of corrected relative phase angle samples;

    h) an integrate and dump filter (IDF) coupled to the modulo-2π

    correction circuit for receiving the corrected relative phase angle samples and sum them over each symbol period, then creating an output signal from the sums, each sum representing a decoded phase angle for the current symbol;

    i) a four-phase decoder circuit coupled to the IDF circuit for receiving the decoded phase angle of the symbol and for decoding the angle into a pair of decoded bits; and

    j) an adjustment circuit coupled to receive the signal sent to the four-phase decoder circuit for calculating a decoding error between the decoded phase angle for each symbol in a preamble and a respective one of a predetermined set of phase angles stored by the adjustment circuit, and for adjusting the sample timing and carrier phase adjustment to minimize the decoding error.

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