Method and apparatus for cost-based heuristic instruction scheduling
First Claim
1. A method for cost-based heuristic instruction scheduling instructions for execution in a pipelined processor, said instructions comprising definitions, resources for use in said pipeline processor, or definitions and resources for use in said pipelined processor, said method comprising the steps of:
- building an instruction dependency graph data structure for an instruction block, said instruction block comprising a plurality of instructions to be scheduled and said dependency graph data structure comprising said plurality of instructions arranged in a serial relationship such that a higher level instruction will precede a lower level instruction when definitions or use of a resource of said higher level instruction are necessary for said pipelined processor to execute said lower level instruction;
accessing free instructions in said instruction dependency graph data structure, said free instructions comprising instructions that do not have a higher preceding instruction;
building a free instruction list data structure comprising said free instructions;
providing a plurality of component modeling means for determining a plurality of cost heuristics for said pipelined processor;
simulating clock cycles and instruction execution in said pipelined processor for each of said free instructions so as to determine a plurality of cost heuristics by accessing said component modeling means for said plurality of cost heuristics;
computing a total cost for each free instruction by summing said plurality of cost heuristics;
building a cost table data structure comprising said total cost for each free instruction; and
scheduling for execution in said pipelined processor one of said free instructions based on a lowest total cost in said cost table data structure wherein execution time pipeline interlocks in said pipelined processor are reduced thereby improving execution speed in said pipelined processor for said plurality of instructions in said instruction block.
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Abstract
A method and apparatus for cost based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. The method and apparatus schedules instructions of an instruction block one at a time, based on the lowest total cost among all the current eligible free instructions. The total cost of each of the current eligible free instructions is computed based on the weighted sum of a plurality of cost heuristics. The cost heuristics used in the preferred embodiment comprise a resource dependency cost, a data dependency cost, a dependency wait cost, a dependent cycle cost, a floating point ratio cost, a store ratio cost and a floating point queue cost. Additionally, in the preferred embodiment, a number of the cost heuristics are modeled by a processor model. As a result, improved overall effectiveness in speeding up the execution time of an instruction block is achieved.
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Citations
34 Claims
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1. A method for cost-based heuristic instruction scheduling instructions for execution in a pipelined processor, said instructions comprising definitions, resources for use in said pipeline processor, or definitions and resources for use in said pipelined processor, said method comprising the steps of:
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building an instruction dependency graph data structure for an instruction block, said instruction block comprising a plurality of instructions to be scheduled and said dependency graph data structure comprising said plurality of instructions arranged in a serial relationship such that a higher level instruction will precede a lower level instruction when definitions or use of a resource of said higher level instruction are necessary for said pipelined processor to execute said lower level instruction; accessing free instructions in said instruction dependency graph data structure, said free instructions comprising instructions that do not have a higher preceding instruction; building a free instruction list data structure comprising said free instructions; providing a plurality of component modeling means for determining a plurality of cost heuristics for said pipelined processor; simulating clock cycles and instruction execution in said pipelined processor for each of said free instructions so as to determine a plurality of cost heuristics by accessing said component modeling means for said plurality of cost heuristics; computing a total cost for each free instruction by summing said plurality of cost heuristics; building a cost table data structure comprising said total cost for each free instruction; and scheduling for execution in said pipelined processor one of said free instructions based on a lowest total cost in said cost table data structure wherein execution time pipeline interlocks in said pipelined processor are reduced thereby improving execution speed in said pipelined processor for said plurality of instructions in said instruction block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An apparatus for scheduling cost-based heuristic instructions for execution in a pipelined processor, said instructions comprising definitions, resources for use in said pipeline processor, or definitions and resources for use in said pipelined processor, said apparatus comprising:
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a driver means for driving said cost-based heuristic instruction scheduling for an instruction block comprising a plurality of instructions to be scheduled, said driver means comprising an interface for receiving said instruction block; a dependency graph building means coupled to said driver means for building an instruction dependency graph data structure for said instruction block, said instruction dependency graph data structure comprising said plurality of instructions arranged in a serial relationship such that a higher level instruction will precede a lower level instruction when definitions or use of a resource of said higher level instruction are necessary for said pipelined processor to execute said lower level instruction; a list building means coupled to said driver means for building a free instruction list data structure for said instructions, said free instructions comprising said instructions in said dependency graph data structure which do not have a higher level preceding instruction; and processor modeling means for modeling said plurality of cost heuristics, said processor modeling means comprising a time passage simulation means and a plurality of component modeling means, said time passage simulation means simulates clock cycles and instruction execution in said pipelined processor for said free instruction based on said component modeling means for said free instruction to ascertain a plurality of cost heuristics, said processor modeling means being initialized for said instruction block; a scheduling means coupled to said driver means and said processor modeling means for scheduling one of said free instructions, said scheduling means computing a total cost for each free instruction by summing said plurality of cost heuristics and scheduling for execution in said pipelined processor one of said free instructions based on a lowest total cost wherein execution time pipeline interlocks in said pipelined processor are reduced thereby improving execution speed in said pipelined processor for said plurality of instructions in said instruction block. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification