Programmable interconnect structure for logic blocks

• US 5,204,556 A
• Filed: 05/06/1991
• Issued: 04/20/1993
• Est. Priority Date: 05/06/1991
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Shankar, Kapil
• Primary Examiner(s): Hudspeth, David R.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/696,462
• Time in Patent Office: 715 Days
• Field of Search: 307/465, 307/465.1, 307/482.1, 307/303, 307/303.1
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A structure for making programmable connections between the input and output terminals of individual logic blocks in a logic device is disclosed. In one embodiment, each output terminal is programmably connected to only one input terminal of each logic block. The same principle is followed in making connections between the input pins of the device and the input terminals of the logic blocks.

Claims

1. A programmable interconnect structure comprising:

a plurality of logic blocks, each of said logic blocks having a plurality of input terminals and a plurality of output terminals, the number of output terminals of each logic block being less than the number of input terminals of said logic block;

an input channel to each of said one or more logic blocks, each input channel comprising a plurality of input lines connected to predetermined input terminals of a predetermined one of said logic blocks;

a plurality of signal routing channels, each of said signal routing channels comprising a plurality of signal routing lines;

said logic blocks being grouped into one or more megacells, each of said megacells containing more than one logic block, the output terminals of the logic blocks in each of said megacells being connected to predetermined signal routing lines in a predetermined one of said signal routing channels; and

a matrix of programmable connections between each of said input channels and each of said signal routing channels wherein the number of said programmable connections in each said matrix is less than the number of input lines in said matrix multiplied by the number of signal routing lines in said matrix and equal to or greater than the number of input lines in said matrix.

2. The programmable interconnect structure of claim 1 wherein the number of output terminals of the logic blocks in each of said megacells is equal to the number of input terminals of each of said logic blocks.

3. The programmable interconnect structure of claim 1 wherein each of said signal routing lines is programmably connected to only one of said input lines in each of said input channels.

4. The programmable interconnect structure of claim 1 comprising a plurality of device terminals, said device terminals being separated into groups, the device terminals in each of said groups being connected through input/output cells to predetermined signal routing lines in a predetermined one of said signal routing channels.

5. The programmable interconnect structure of claim 1 comprising a plurality of resource routing lines and a plurality of device terminals, predetermined ones of said output terminals being programmably connectable to predetermined ones of said resource routing lines, predetermined ones of said resource routing lines being connected through input/output cells to predetermined ones of said device terminals.

6. The programmable interconnect structure of claim 1 comprising:

a plurality of device terminals, said device terminals being separated into groups, the device terminals in each of said groups being connected through input/output cells to predetermined signal routing lines in a predetermined one of said signal routing channels; and

a plurality of resource routing lines, predetermined ones of said output terminals being programmably connectable to predetermined ones of said resource routing lines, predetermined ones of said resource routing lines being connected through input/output cells to predetermined ones of said device terminals.

7. A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and a plurality of device terminals, wherein each of said output lines is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.

8. A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and

a plurality of device terminals,

wherein each of said device terminals is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.

9. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks is in the sum of the products form.

10. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals though input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a programmable logic device (PLD).

11. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a programmable array logic/generic array logic circuit (PAL/GAL).

12. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a programmable logic array (PLA).

13. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said input routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a random access memory (RAM).

14. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a programmable read only memory (PROM).

15. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said control routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises an erasable programmable read only memory (EPROM).

16. A programmable logic device comprising;

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises an electrically erasable programmable read only memory (EEPROM).

17. A programmable logic device comprising:

a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks;

wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and

wherein at least one of said logic blocks comprises a combination of multiplexers.

18. A programmable logic device comprising:

a plurality of logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals;

a plurality of device terminals;

an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, wherein one, and only one, of said programmable connections need be programmed in order to connect one of said output terminals to one of said device terminals.

19. The programmable logic device of claim 18 wherein at least one of said output terminals is programmably connectable via said output routing resource arrangement to two or more of said device terminals simultaneously.