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Programmable interconnect structure for logic blocks

  • US 5,204,556 A
  • Filed: 05/06/1991
  • Issued: 04/20/1993
  • Est. Priority Date: 05/06/1991
  • Status: Expired due to Fees
First Claim
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1. A programmable interconnect structure comprising:

  • a plurality of logic blocks, each of said logic blocks having a plurality of input terminals and a plurality of output terminals, the number of output terminals of each logic block being less than the number of input terminals of said logic block;

    an input channel to each of said one or more logic blocks, each input channel comprising a plurality of input lines connected to predetermined input terminals of a predetermined one of said logic blocks;

    a plurality of signal routing channels, each of said signal routing channels comprising a plurality of signal routing lines;

    said logic blocks being grouped into one or more megacells, each of said megacells containing more than one logic block, the output terminals of the logic blocks in each of said megacells being connected to predetermined signal routing lines in a predetermined one of said signal routing channels; and

    a matrix of programmable connections between each of said input channels and each of said signal routing channels wherein the number of said programmable connections in each said matrix is less than the number of input lines in said matrix multiplied by the number of signal routing lines in said matrix and equal to or greater than the number of input lines in said matrix.

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