Digital signal level translator

• US 5,204,557 A
• Filed: 10/15/1991
• Issued: 04/20/1993
• Est. Priority Date: 10/15/1991
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Nguyen, Thai M.
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/776,838
• Time in Patent Office: 553 Days
• Field of Search: 307/443, 307/451, 307/475, 307/494, 307/496-497, 307/500-501
• US Class Current: 326/81
• CPC Class Codes: H03K 3/356017 using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A low static power, digital signal level translator for translating an unbalanced digital signal to a balanced digital signal with a greater dynamic signal range includes two complementary MOSFET latches and a complementary MOSFET output buffer amplifier. The two latches each receive an unbalanced digital input signal (e.g. with TTL voltage levels) and translate it to a second unbalanced digital signal and an asymmetrically balanced digital signal. The symmetrically biased, output buffer amplifier receives these signals and produces therefrom a symmetrically balanced digital output signal with a greater dynamic signal range (e.g. with ±10 volt levels). Various embodiments include two gate-driven complementary MOSFET latches, two source-driven complementary MOSFET latches or a combination of gate-driven and source-driven complementary MOSFET latches, each of which includes a pair of cross-coupled complementary MOSFET totem-pole amplifiers, for providing the second unbalanced digital signal and the asymmetrically balanced digital signal. Each embodiment further includes a complementary MOSFET totem-pole output buffer amplifier as the symmetrically biased, output buffer amplifier for providing the symmetrically balanced digital output signal.

Claims

1. A digital signal level translator for translating an unbalanced digital signal to a balanced digital signal, said digital signal level translator comprising:

first translator means for receiving and translating a first unbalanced digital signal to a second unbalanced digital signal, wherein said first unbalanced digital signal has a first unbalanced dynamic signal range bounded by a first level and a reference level, and wherein said second unbalanced digital signal has a second unbalanced dynamic signal range bounded by a second level and said reference level;

second translator means for receiving and translating said first unbalanced digital signal to a first balanced digital signal, wherein said first balanced digital signal has a first balanced dynamic signal range bounded by said first level and a third level; and

output buffer means for receiving said second unbalanced digital signal and said first balanced digital signal, and for providing a second balanced digital signal, wherein said second balanced digital signal has a second balanced dynamic signal range bounded by said second level and said third level;

wherein said first and second levels have a first polarity relative to said reference level, and said third level has a second polarity relative to said reference level.

2. A digital signal level translator as recited in claim 1, further comprising inverter means coupled to said first and second translator means for receiving and inverting said first unbalanced digital signal.

3. A digital signal level translator as recited in claim 1, wherein said first translator means comprises a first gate-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

4. A digital signal level translator as recited in claim 1, wherein said second translator means comprises a second gate-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

5. A digital signal level translator as recited in claim 1, wherein said first translator means comprises a first source-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

6. A digital signal level translator as recited in claim 1, wherein said second translator means comprises a second source-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

7. A digital signal level translator as recited in claim 1, wherein said output buffer means comprises a complementary MOSFET totem-pole buffer amplifier including a first MOSFET for receiving said second unbalanced digital signal and a complementary second MOSFET for receiving said first balanced digital signal.

8. A digital signal level translation method for translating an unbalanced digital signal to a balanced digital signal, said digital signal level translation method comprising the steps of:

receiving a first unbalanced digital signal having a first unbalanced dynamic signal range bounded by a first level and a reference level;

translating said first unbalanced digital signal to a second unbalanced digital signal having a second unbalanced dynamic signal range bounded by a second level and said reference level;

translating said first unbalanced digital signal to a first balanced digital signal having a first balanced dynamic signal range bounded by said first level and a third level;

combining said second unbalanced digital signal and said first balanced digital signal to provide a second balanced digital signal having a second balanced dynamic signal range bounded by said second level and said third level;

wherein said first and second levels have a first polarity relative to said reference level, and said third level has a second polarity relative to said reference level.

9. A digital signal level translation method as recited in claim 8, further comprising the step of inverting said first unbalanced digital signal.

10. A digital signal level translation method as recited in claim 8, wherein said step of translating said first unbalanced digital signal to a second unbalanced digital signal comprises inputting said first unbalanced digital signal into and outputting said second unbalanced digital signal from a first gate-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

11. A digital signal level translation method as recited in claim 8, wherein said step of translating said first unbalanced digital signal to a first balanced digital signal comprises inputting said first unbalanced digital signal into and outputting said first balanced digital signal from a second gate-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

12. A digital signal level translation method as recited in claim 8, wherein said step of translating said first unbalanced digital signal to a second unbalanced digital signal comprises inputting said first unbalanced digital signal into and outputting said second unbalanced digital signal from a first source-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

13. A digital signal level translation method as recited in claim 8, wherein said step of translating said first unbalanced digital signal to a first balanced digital signal comprises inputting said first unbalanced digital signal into and outputting said first balanced digital signal from a second source-driven complementary MOSFET latch including a pair of cross-coupled complementary MOSFET totem-pole amplifiers.

14. A digital signal level translation method as recited in claim 8, wherein said step of combining said second unbalanced digital signal and said first balanced digital signal to provide a second balanced digital signal comprises inputting said second unbalanced digital signal and said first balanced digital signal into first and second complementary MOSFETs, respectively, of a complementary MOSFET totem-pole buffer amplifier, and further comprises outputting therefrom said second balanced digital signal.