Method and apparatus for controlling clock skew

• US 5,204,559 A
• Filed: 01/23/1991
• Issued: 04/20/1993
• Est. Priority Date: 01/23/1991
• Status: Expired due to Term

• Current Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Original Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Inventors: Deyhimy, Ira, Hedges, David W., Terrell, William C., Deming, Robert N.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/645,981
• Time in Patent Office: 818 Days
• Field of Search: 307/262, 307/269, 307/597, 307/480, 307/526, 307/527, 307/202.1
• US Class Current: 327/232
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00091 using fuse links
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/1502 programmable

Abstract

A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the skew between clock outputs is minimized. The delay in each clock output path is determined by measuring the frequency of a ring oscillator created by connecting a feedback loop across the delay elements. The frequency of oscillation is measured as delay elements are switched into or out of each clock output path until the frequency reaches close to a target frequency.

Claims

1. A clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal and a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said clock distribution circuit comprising:

for each master clock output line, means for generating a time delay between said primary clock signal and said master clock signal on said master clock output line, said time delay generating means comprising a series of delay elements, each of said series of delay elements further including one or more subseries of delay elements, each said subseries of delay elements for generating a portion of said time delay, and each of said subseries coupled to a switching means, said switching means for controlling whether said subseries provides said portion of said time delay, said switching means including a fuse;

means for automatically controlling said time delay generated by said time delay generating means for ensuring that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range; and

means for emulating a fuse in its blown state before said fuse is blown.

2. A clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal and a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said clock distribution circuit comprising:

for each master clock output line, means for generating a time delay between said primary clock signal and said master clock signal on said master clock output line, said time delay generating means comprising a series of delay elements, each of said series of delay elements further including one or more subseries of delay elements, each said subseries of delay elements for generating a portion of said time delay, and each of said subseries coupled to a switching means, said switching means for controlling whether said subseries provides said portion of said time delay, said switching means comprising a transistor; and

means for automatically controlling said time delay generated by said time delay generating means for ensuring that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range.

3. A clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal and a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said clock distribution circuit comprising:

for each master clock output line, means for generating a time delay between said primary clock signal and said master clock signal on said master clock output line, said time delay generating means additionally comprising a feedback loop connected across said time delay generating means, said feedback loop for generating an oscillating signal having a frequency inversely proportional to said time delay; and

means for automatically controlling said time delay generated by said time delay generating means for ensuring that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range.

4. The clock distribution circuit of claim 3, further comprising means for measuring the frequency of said oscillating signal.

5. The clock distribution circuit of claim 4, wherein said frequency measuring means comprises a tester.

6. A clock distribution system in a digital logic system, said clock distribution system producing one or more master clock output signals from a primary clock signal, said clock distribution system for allowing automatic adjustment of delay between said primary clock signal and each master clock output signal, said clock distribution system comprising:

one or more master clock driver circuits, each master clock driver circuit having a plurality of delay elements, said delay elements being grouped into blocks wherein a first delay block contains one delay element, a second delay block contains two delay elements, a third delay block contains four delay elements, and a fourth delay block contains eight delay elements, each master clock output signal being generated by a separate one of said master clock driver circuits; and

one or more switching means in each master clock driver circuit, said switching means for allowing one or more delay blocks to be switched into or switched out of said master clock driver circuit in order to increase or decrease the delay between said primary clock signal and said master clock output signal from said master clock driver circuit.

7. A clock distribution system in a digital logic system, said clock distribution system producing one or more master clock output signals from a primary clock signal, said clock distribution system for allowing automatic adjustment of delay between said primary clock signal and each master clock output signal, said clock distribution system comprising:

one or more master clock driver circuits, each master clock driver circuit having a plurality of delay elements, each master clock output signal being generated by a separate one of said master clock driver circuits; and

one or more switching means in each master clock driver circuit, said switching means for allowing one or more delay elements to be switched into or switched out of said master clock driver circuit in order to increase or decrease the delay between said primary clock signal and said master clock output signal from said master clock driver circuit, said switching means including a read only memory (ROM).

8. A clock distribution system in a digital logic system, said clock distribution system producing one or more master clock output signals from a primary clock signal, said clock distribution system for allowing automatic adjustment of delay between said primary clock signal and each master clock output signal, said clock distribution system comprising:

one or more master clock driver circuits, each master clock driver circuit having a plurality of delay elements, each master clock output signal being generated by a separate one of said master clock driver circuits; and

one or more switching means in each master clock driver circuit, said switching means for allowing one or more delay elements to be switched into or switched out of said master clock driver circuit in order to increase or decrease the delay between said primary clock signal and said master clock output signal from said master clock driver circuit, said switching means including a random access memory (RAM).

9. A clock distribution system in a digital logic system, said clock distribution system producing one or more master clock output signals from a primary clock signal, said clock distribution system for allowing automatic adjustment of delay between said primary clock signal and each master clock output signal, said clock distribution system comprising:

one or more master clock driver circuits, each master clock driver circuit having a plurality of delay elements, each master clock output signal being generated by a separate one of said master clock driver circuits;

one or more switching means in each master clock driver circuit, said switching means for allowing one or more delay elements to be switched into or switched out of said master clock driver circuit in order to increase or decrease the delay between said primary clock signal and said master clock output signal from said master clock driver circuit; and

a feedback path connected between the output of said master clock driver circuit and the input of said master clock driver circuit such that the feedback path generates a ring oscillator having a frequency inversely proportional to the delay between said primary clock signal and said master clock output signal.

10. A method for setting delays in a clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal, a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said method comprising the steps of:

for each master clock output line, generating a time delay between said primary clock signal and said master clock signal on said master clock output line by a series of delay elements;

dividing each of said series of delay elements into one or more subseries of delay elements, each said subseries of delay elements thereby generating a portion of said generated time delay;

coupling each of said subseries to a switching means, said switching means thereby controlling whether said subseries provides said portion of said generated time delay by blowing one or more fuses;

automatically controlling said time delay generated by said time delay generating means to ensure that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range; and

emulating a fuse in its blown state before said fuse is blown.

11. A method for setting delays in a clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal, a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said method comprising the steps of:

for each master clock output line, generating a time delay between said primary clock signal and said master clock signal on said master clock output line, said time delay generating step including the step of connecting a feedback loop across a time delay generating means, thereby generating an oscillating signal having a frequency inversely proportional to the generated time delay; and

automatically controlling said time delay generated by said time delay generating means to ensure that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range.

12. The method of claim 11, further comprising the step of measuring the frequency of said oscillating signal.

13. A method for automatically adjusting delay between a primary clock signal and each of one or more clock output signals in a clock distribution system in a digital logic system, said clock distribution system producing one or more master clock output signals from said primary clock signal, said clock distribution circuit comprising one or more master clock driver circuits, each master clock driver circuit having a plurality of delay elements, each master clock output signal being generated by a separate one of said master clock driver circuits, said method comprising the steps of:

setting one or more switching means in each master clock driver circuit, said switching means for allowing one or more delay elements to be switched into or switched out of said master clock driver circuit in order to increase or decrease the delay between said primary clock signal and said master clock output signal from said master clock driver circuit; and

connecting a feedback path between the output of said master clock driver circuit and the input of said master clock driver circuit such that the feedback path generates a ring oscillator having a frequency inversely proportional to the delay between said primary clock signal and said master clock output signal.

14. A clock distribution circuit

for use in a digital logic system, said digital logic system including a primary clock signal and a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said clock distribution circuit comprising:

for each master clock output line, means for generating a time delay between said primary clock signal and said master clock signal on said master clock output line;

means for automatically controlling said time delay generated by said time delay generating means for ensuring that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range;

means for measuring the difference between a target time delay and said time delay generated by said time delay generating means; and

means for adjusting said time delay generating means by using said measured differences in a look-up table to determine an adjustment to bring said time delay generated by said time delay generating means closer to said target time delay.

15. A method for setting delays in a clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal, a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said method comprising the steps of:

for each master clock output line, generating a time delay between said primary clock signal and said master clock signal on said master clock output line;

automatically controlling said time delay generated by said time delay generating means to ensure that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range;

measuring the difference between a target time delay and said generated time delay; and

adjusting said generated time delay by using said measured difference in a look-up table to determine an adjustment to bring said generated time delay closer to said target time delay.