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Method and apparatus for controlling clock skew

  • US 5,204,559 A
  • Filed: 01/23/1991
  • Issued: 04/20/1993
  • Est. Priority Date: 01/23/1991
  • Status: Expired due to Term
First Claim
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1. A clock distribution circuit for use in a digital logic system, said digital logic system including a primary clock signal and a plurality of digital logic system components, said clock distribution circuit producing from said primary clock signal a plurality of master clock signals on a plurality of master clock output lines, one or more of said digital logic system components receiving a master clock signal on one of said master clock output lines, said clock distribution circuit comprising:

  • for each master clock output line, means for generating a time delay between said primary clock signal and said master clock signal on said master clock output line, said time delay generating means comprising a series of delay elements, each of said series of delay elements further including one or more subseries of delay elements, each said subseries of delay elements for generating a portion of said time delay, and each of said subseries coupled to a switching means, said switching means for controlling whether said subseries provides said portion of said time delay, said switching means including a fuse;

    means for automatically controlling said time delay generated by said time delay generating means for ensuring that differences among delays between said primary clock signal and said master clock signals on said master clock output lines are within a predetermined time range; and

    means for emulating a fuse in its blown state before said fuse is blown.

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