System for high-speed measurement and sorting of particles

• US 5,204,884 A
• Filed: 03/18/1991
• Issued: 04/20/1993
• Est. Priority Date: 03/18/1991
• Status: Expired due to Fees

• Current Assignee: University of Rochester
• Original Assignee: University of Rochester
• Inventors: Leary, James F., Corio, Mark A., McLaughlin, Scott R.
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Ouellette, Scott A.
• Application Number:
  US07/671,009
• Time in Patent Office: 764 Days
• Field of Search: 377/10, 377/12
• US Class Current: 377/10
• CPC Class Codes: B07C 5/3425 of granular material, e.g. ore particles, grain investigation moving fluids or granular solids using optical means G01N21/85
• CPC Class Codes: G01N 15/1456 without spatial resolution of the texture or inner structure of the particle, e.g. processing of pulse signals
• CPC Class Codes: G01N 15/149 specially adapted for sorting particles, e.g. by their size or optical properties
• CPC Class Codes: Y10S 209/906 Pneumatic or liquid stream feeding item
• CPC Class Codes: Y10T 436/10 Composition for standardization, calibration, simulation, stabilization, preparation or preservation; processes of use in preparation for chemical testing

Abstract

A system for sorting particles is arranged such that the presence or absence of multiple parameters is determined for each particle in a flow of particles, and a logic condition is determined based on the multiple parameters. Thereafter, particles are outputted from the system when the logic condition is present. Accordingly, multiparameter high-speed measurements of a rare subpopulation of particles (e.g. biological cells) can be made amidst a larger population of particles with differing characteristics. When attached to a multiparameter flow cytometer/cell sorter and microcomputer, the system allows multiparameter analysis of cells at rates in excess of 100,000 cells/sec. This system can be an outboard module attached to a commercially available or home-built flow cytometer.

Claims

1. A particle sorter for counting and sorting a plurality of detection signals of a particle detector comprising:

a source of detection signals for respective particle parameters;

reference voltage means for developing a plurality of reference voltages;

comparator means for comparing each of said detection signals with a respective one of said reference voltages;

said comparator means generating a respective compared pulse when a detection signal exceeds a respective reference voltage;

counting means each actuated by compared pulses for a respective particle parameter for counting said compared pulses;

delay means for delaying said detection signals by a predetermined delay interval to thereby generate delayed detection signals;

logic means receiving said respective compared pulse signals and producing a logic signal whenever a selected combination of said respective compared pulses occurs during said predetermined delay interval;

gate means responsive to said logic signal for selectively allowing said delayed detection signals to pass through said gate means in response to said logic signal and for preventing said delayed detection signals from passing through said gate means in the absence of said logic signal.

2. A particle sorter as in claim 1 in which said logic means comprises logic timing means for determining said predetermined delay interval in response to one of said compared pulses and gate timing means for applying said logic signal to said gate means at a predetermined time.

3. A particle sorter as in claim 2 further comprising latching means coupled to said comparator means and said logic means for receiving said compared pulses and latching said compared pulses.

4. A particle sorter as in claim 3 further comprising a logic latching means coupled to said logic means, said logic timing means and said gate timing means for receiving said logic signal and latching said logic signal upon receiving a clocking and reset signal from said logic timing means at the end of said predetermined delay interval and resetting said latching means in response to said clocking and reset signal from said logic timing means.

5. A particle sorter of claim 4 further comprising output means coupled to said gate means for buffering said delayed detection signals which pass through said gate means.

6. A particle sorter of claim 5 further comprising input means coupled to said source of detection signals, said comparator means and said delay means for buffering and applying said detection signals to said comparator means and said delay means.

7. A method for sorting particles comprising:

applying a plurality of detection signals from a plurality of particle detectors to a delay circuit and respective comparators, said delay circuit effecting in said detection signals a predetermined delay in time and thereby producing delayed input signals;

comparing in said comparators the respective detection signals with respective thresholds producing respective compared pulse signals when respective detection signals meet respective thresholds;

determining a logic condition within said predetermined delay in time in response to said compared pulse signals and thereby producing a gate control signal;

gating said delayed input signals to an output means in response to said gate control signal.

8. A method as in claim 7 further comprising a step of applying said compared pulse signals to a count means for counting said compared pulse signals for the respective detection signals.

9. A particle sorter for sorting a plurality of detection signals of a particle detector comprising:

a reference voltage generator for generating a plurality of reference voltages of predetermined values;

a plurality of comparators each comparing a respective detection signal with a respective reference voltage and producing a respective compared pulse signal when a detection signal has a defined relationship with the reference voltage;

a delay circuit responsive to said plurality of detection signals for effecting in said detection signals a pre-determined delay in time to thereby generate delayed detection signals;

a logic control circuit connected to receive said compared pulse signals within a selected time window and to compare said received compared pulse signals to a logic condition and to produce a logic control signal whenever said compared pulse signals meet said logic condition; and

a plurality of gates connected to receive said delayed detection signals and to receive said logic control signal and to open in response to said logic control signal, passing said delayed detection signals through said gates and to stay closed when said logic control signal is absent.

10. A particle sorter as in claim 9 further comprising a plurality of pulse counters associated with said plurality of comparators and each of said plurality of counters responsive to one of said comparators for counting a number of compared pulses.

11. A particle sorter as in claim 10 in which said logic circuit comprises a logic timing circuit for determining said predetermined delay in time in response to one of said compared pulses and a gate timing circuit for receiving said logic signal and applying said logic signal to said gate means at a predetermined time.

12. A particle sorter as in claim 11 in which said logic timing circuit generates a latch and reset signal at the end of said predetermined delay in time.

13. A particle sorter as in claim 12 further comprising a plurality of first latches, each of said plurality of first latches coupled to one of said plurality of comparators for latching one of said compared pulse signals and a second latch coupled to said logic control circuit for latching said logic control signal, said plurality of first latches being reset and said second latch being latched in response to said latch and reset signal.

14. A particle sorter as in claim 13 further comprising a plurality of output buffers coupled to said plurality of gates for receiving said delayed detection signals and for buffering said delayed detection signals.

15. A particle sorter as in claim 14 further comprising input buffers coupled to said plurality of detection signals, said plurality of comparators and said delay circuit for buffering said plurality of detection signals and for applying said plurality of detection signals to said plurality of comparators and to said delay circuit.

16. A particle sorter of claim 15 further comprising a logic condition counter, associated with said logic control circuit, responsive to said logic control signal for counting the logic control signal.

17. A particle sorter as in claim 16 further Comprising a data acquisition system coupled to said output buffers for processing said delayed detection signals.

19. A particle sorter as in claim 17 further comprising a pulse generating means coupled to said plurality of gates for applying to said data acquisition system reference pulses having an amplitude equal to respective of said plurality of reference voltages and amplifying means coupled to said output buffers and said data acquisition system for receiving said plurality of reference voltages and amplifying said plurality of reference voltages to determine the amplitude of said plurality of reference voltages relative to said detection signals.

20. A particle sorter as in claim 19 in which said amplifying means comprises linear amplification circuitries.

21. A particle sorter as in claim 19 in which said amplifying means comprises non-linear amplification circuitries.

22. A particle sorter as in claim 19 in which one of said plurality of reference voltages comprises a doublet threshold voltage said particle sorter further comprising a doublet comparator for comparing said doublet threshold voltage to said total signal producing a doublet compared pulse when a total detection signal has a defined relationship with said doublet threshold voltage and a doublet pulse counter for measuring a coincident condition and for adjusting said reference voltage values in response to said doublet counter value.

18. A particle sorter for counting and sorting particles comprising:

a first particle detector generating a plurality of detection signals of said first particle detector;

a second particle detector generating a plurality of detection signals of said second particle detector;

reference voltage means for developing a plurality of reference voltages of predetermined values;

comparator means for comparing each of said detection signals of said first particle detector with a respective one of said plurality of reference voltages;

said comparator means generating respective compared pulses when said each of said detection signals of said first particle detector is at least as great as said respective one of said plurality of reference voltages during a predetermined delay in time;

a plurality of counting means each actuated by one of said respective compared pulses for counting said compared pulses;

logic means receiving said respective compared pulses and producing a logic signal whenever one or more of said respective compared pulses occurs during said predetermined delay interval;

gate means responsive to said logic signal for selectively allowing said detection signals of said second particle detector to pass through said gate means in response to said logic signal and for preventing said detection signals of said second particle detector from passing through said gate means in the absence of said logic signal.