Duplex processor arrangement for a switching system

• US 5,204,952 A
• Filed: 07/23/1991
• Issued: 04/20/1993
• Est. Priority Date: 07/18/1988
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: Ayers, David J., Guttman, Jacob
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US07/734,033
• Time in Patent Office: 637 Days
• Field of Search: 395/550, 395/575
• US Class Current: 714/48
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

The invention provides a duplex processor arrangement wherein the processors are only pseudo-synchronized to each other. Each processor is provided with its own independent clock circuit and the two clock circuits operate at the same nominal frequency. A circuit means is provided for periodically forcing a rendezvous between processors whereat a controller circuit ensures that the processors have processed the same information since the last rendezvous. Each processor comprises a match circuit including memory means connected to store address/data information related to instructions performed by the processors. Each match circuit compares the information from the processors and generates an alarm signal upon a mismatch.

Claims

1. A method of controlling a duplex processor arrangement comprising a pair of computing circuits each comprising a processor portion and a control portion, the processor portion including a microprocessor and an associated instruction cache memory and the control portion comprising a maintenance controller, a match circuit, and an interrupt controller, the maintenance controller, match circuit and interrupt controller of each computing circuit being responsively interconnected to each other and connected to their respective processor portion as well as to respective mate circuits in the other of the computing circuits, the control portion also including an instruction counter for cyclically counting to a predetermined number instructions executed by its respective microprocessor, each of the computing circuits being driven from a respective independent clock circuit, the method comprising the steps of,

each of the instruction counters counting the instructions executed by its associated microprocessor,

the instruction counter to first reach the predetermined number generating a flag signal, and, the maintenance control associated with that instruction counter responding to the flag signal by inhibiting execution of further instructions by its associated microprocessor until the instruction counter of the other computing circuit has also reached the predetermined number whereby a rendezvous between the computing circuits has occurred, the inhibiting step being achieved by the maintenance controller responsive to the flag signal generating an instruction cache disable signal that causes a cache-miss cycle to occur at the processor instruction that is coincident with the flag signal and for preventing completion of the cache-miss cycle until the match circuits of the computing circuits and the maintenance controller associated with the instruction counter to first reach the predetermined number have determined that the computing circuits are at the same point in the software processing stream.

2. A method as defined in claim 1 wherein each match circuit comprises buffer memories for storing data/address information related to a predetermined number of instructions performed by both computing circuits and comprising the further steps of, writing the buffer memories independently from one another and reading them out together to a comparing circuit as successive entries are matched.

3. A method as defined in claim 2 wherein each match circuit provides an alarm signal to its respective maintenance controller thereby to initiate maintenance procedures whenever a mismatch between the data/address information in the buffer memories is detected, the method further comprising the step of continuously comparing memory entries between rendezvous.

4. A method as defined in claim 3 and comprising the additional step of exclusive-ORRING the data/address information related to every instruction before storing it in the buffer memories of the match circuits.

5. A method as defined in claim 4 and comprising the further step of storing the addresses of the related exclusive-ORRED information in a separate buffer memory in the match circuits thereby enabling the generation of the original data information.

6. A method as defined in claim 1 wherein each maintenance controller has the capability of recognizing whether data on the address bus of its associated computing circuit designates an access to either an input/output port or to system memory, the method comprising the further steps of, on identification by a maintenance controller of an instruction related to an access to an input/output port, inhibiting the completion of that instruction until the match circuits of the computing circuits and the maintenance controller that identified the instruction related to an access to an input/output port have determined that the computing circuits are at the same point in the software processing stream and, resuming processing of instructions.

7. A method as defined in claim 6 and comprising the further step of resetting the instruction counter in each computing circuit upon the completion of an input/output access instruction.

8. A method as defined in claim 1 comprising the steps of continuously comparing the two sets of data resulting from the instructions executed by both computing circuits when the data becomes available and generating an alarm signal upon a mismatch therebetween.