Method of making single layer personalization

• US 5,206,184 A
• Filed: 11/15/1991
• Issued: 04/27/1993
• Est. Priority Date: 11/15/1991
• Status: Expired due to Term

• Current Assignee: Silicon Engineering, Inc. (Creative Technology Ltd.)
• Original Assignee: Sequoia Semiconductor, Inc.
• Inventors: Hansen, Richard B., Venes, Keith R., Allen, Joanne M., Wolski, Guntram K.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/792,586
• Time in Patent Office: 529 Days
• Field of Search: 437/8, 437/48, 437/51, 437/52, 437/180, 437/204, 437/205, 437/206, 148/DIG. 8, 148/DIG. 20
• US Class Current: 438/587
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/02 Contacts, special

Abstract

A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.

Claims

1. A process for fabricating an electrical connection between base cells of different rows in a gate array comprising the steps of:

providing a gate array having rows of base cells, wherein a space is between said rows, wherein columns of segments of a first conductive layer are fabricated between the rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments

determining a connection path for coupling said base cells of different rows in said gate array, such that said connection path comprises a plurality of said segments of said first conductive layer; and

coupling said segments of said connection path using the vias of said path segments and a second conductive layer, such that said base cells of different rows are coupled at said second conductive layer utilizing a portion of said first conductive layer.

2. The process as defined in claim 1 wherein said columns of segments are aligned substantially vertical in said space, such that they are substantially perpendicular to said rows.

3. The process as defined in claim 1 wherein said path comprises sections, said sections being either horizontal or vertical to said rows.

4. In a gate array having parallel rows of base cells, A process for fabricating a connection between base cells of different rows in a gate array comprising the steps of:

providing a gate array having rows of base cells, wherein each base cell comprises a plurality of transistors, wherein a space is between said rows, wherein columns of vertical segments of a first conductive layer are fabricated between the rows, such that said segments are substantially perpendicular to said rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments,

designing a routing path between one of said base cells of different rows, wherein said routing path comprises portions which are vertical and horizontal to said rows; and

coupling said base cells of different rows, wherein said vertical portions of said routing path comprise said vertical segments coupled together with a second conductive material using their respective vias, such that said base cells of different rows are coupled at said second conductive layer by using a portion of said first conductive layer.

5. The process defined in claim 4 wherein said vertical segments of different columns are coupled horizontally at said second conductive layer using their respective vias.

6. The process defined in claim 4 further comprising the step of coupling said transistors of each of said base cell to form a first functional logic unit using said vias and said second conductive layer, such that said electrical path and said base cells create a second logic unit when coupled.

7. A process for fabricating a connection between base cells of different rows in a gate array comprising the steps of:

providing a gate array having parallel rows of base cells, wherein a space is between said rows, wherein columns of vertical segments of a first conductive layer are fabricated between the rows, such that said segments are substantially perpendicular to said rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments;

coupling each of said base cells of different rows to one of said vertical segments using a second conductive layer, wherein said second conductive material is connected using said vias;

creating an electrical path between said first and second points, said path consisting of horizontal parts and vertical parts, wherein said horizontal parts consist of said second conductive material and said vertical parts consisting of said vertical segments coupled together by said second conductive material using the respective vias of said vertical segments, the endpoints of said horizontal parts being coupled to the endpoints of said coupled vertical parts using their respective vias, such that said base cells of different rows are coupled at said second conductive layer by using a portion of said first conductive layer.

8. The process as defined in claim 7 further comprising the step of coupling said transistors of each of said base cells to form a first logic unit using said vias and said second conductive layer, such that said electrical path and said base cells create a second logic unit when coupled.

9. The process as defined in claim 7 wherein each of said vertical segments is associated with multiple tracks, wherein each track accommodates one of said horizontal parts.

10. A process for fabricating an electrical connection between base cells of different rows comprising the steps of:

providing a gate array having rows of base cells, wherein said base cells comprise a plurality of transistors, wherein said plurality can be coupled in multiple schemes to perform a simple logic function, wherein a space exists between said rows, wherein segments of a first conductive layer are fabricated between the rows, said array having an insulative layer disposed on said segments, said insulative layer having vias over the base cells and each end of said segments;

designing a logic function consisting of connection path of said segments of said first conductive layer for coupling said base cells of different rows and a connection scheme for coupling said plurality; and

coupling said path segments and said plurality using said vias and a second conductive layer, such that said base cells of different rows are coupled at said second conductive layer utilizing a portion of said first conductive layer.

11. A process for fabricating a base cell for a designated function in a gate array comprising the steps of:

providing a gate array having rows of base cells, wherein each base cell is fabricated to include a plurality of transistors and a plurality of segments of a first conductive material coupled to said plurality of transistors, said cell having an insulative layer disposed on said segments, said insulative layer having vias over each end of said segments, such taht each cell is fabricated up to the via level;

defining a routing path between the transistors of said base cell, wherein said routing path comprises at least one of said segments and at least two of said transistors, such that said cell is capable of performing the designated function when said segments and said are coupled; and

coupling said transistors of the base cells, wherein said portions of said routing path are coupled together with a second conductive material by their respective vias, such that said base cell is fabricated to perform its designated function at said second conductive layer using a portion of said first conductive layer.