Method of processing semiconductor wafers using a contact etch stop

• US 5,206,187 A
• Filed: 12/17/1991
• Issued: 04/27/1993
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Doan, Trung T.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US07/812,063
• Time in Patent Office: 497 Days
• Field of Search: 437/192, 437/200, 437/201, 437/228, 437/194, 437/195, 437/41, 148/DIG. 19, 148/DIG. 147, 357/675, 357/715, 156/656, 156/657
• US Class Current: 438/618
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: Y10S 148/019 Contacts of silicides
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

A method of processing a semiconductor wafer comprises: a) fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations of the wafer; b) providing a layer of transition metal oxide elevationally above the active regions; c) applying an insulating dielectric layer elevationally above the transition metal oxide layer; d) etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and e) etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.

Claims

1. A method of processing a semiconductor wafer comprising the following steps:

fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer;

depositing a layer of transition metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer;

the transition metal layer having a thickness, an outer region and an inner region;

processing the wafer under conditions which reacts a) the transition metal of the inner region over the silicon containing active regions with such silicon to produce a transition metal silicide, and b) the transition metal of the outer region to form a transition metal oxide thereby transforming the outer region over the other areas into transition metal oxide and the transition metal over the silicon containing active regions into sandwich regions of outer transition metal oxide and adjacent transition metal silicide in contact with the active regions;

the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer;

applying an insulating dielectric layer atop the wafer;

selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and

etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.

2. The method of processing a semiconductor wafer of claim 1 wherein the transition metal is selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof.

3. The method of processing a semiconductor wafer of claim 1 wherein the transition metal is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.

4. The method of processing a semiconductor wafer of claim 3 wherein the transition metal is applied to a thickness of about 300 Angstroms.

5. The method of processing a semiconductor wafer of claim 1 wherein,

the transition metal is selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof;

and

the transition metal is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.

6. The method of processing a semiconductor wafer of claim 1 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.

7. The method of processing a semiconductor wafer of claim 6 wherein the step of processing the wafer comprises rapid thermal processing.

8. The method of processing a semiconductor wafer of claim 1 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates;

the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the transition metal, the insulating dielectric deposited over the field effect transistor gates being selected such the transition metal oxide is selectively etchable relative to such insulating dielectric, and wherein the step of etching the transition metal oxide comprises etching the transition metal oxide with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.

9. A method of processing a semiconductor wafer comprising the following steps:

fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer;

depositing a layer of elemental titanium metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer;

the titanium layer having a thickness, an outer region and an inner region;

processing the wafer under conditions which reacts a) the titanium of the inner region over the silicon containing active regions with such silicon to produce a titanium silicide comprising a formula TiSi_x, where "x" is from about 1.0 to 2.5, and b) the titanium of the outer region to form a titanium oxide comprising a formula TiO_y, where "y" is from about 1.0 to 2.0 thereby transforming the outer region over the other areas into TiO_y and the titanium over the silicon containing active regions into sandwich regions of outer TiO_y and adjacent TiSi_x in contact with the active regions;

the outer TiO_y regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer;

applying an insulating dielectric layer atop the wafer;

selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the TiO_y and using the TiO_y as an effective etch stop in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and

etching the TiO_y from the selected portions of outer regions of the sandwich regions.

10. The method of processing a semiconductor wafer of claim 9 wherein the titanium is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.

11. The method of processing a semiconductor wafer of claim 10 wherein the titanium is applied to a thickness of about 300 Angstroms.

12. The method of processing a semiconductor wafer of claim 9 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.

13. The method of processing a semiconductor wafer of claim 9 wherein the step of processing the wafer comprises rapid thermal processing.

14. The method of processing a semiconductor wafer of claim 9 wherein the step of selectively etching the insulating dielectric is conducted with an etchant gas chemistry comprising CHF₃, Ar, and CF₄.

15. The method of processing a semiconductor wafer of claim 9 further comprising etching the TiO_y from the selected portions of outer regions of the sandwich regions with a solution of NH₄ OH or H₂ SO₄.

16. The method of processing a semiconductor wafer of claim 9 wherein,

the step of selectively etching the insulating dielectric is conducted with an etchant gas chemistry comprising CHF₃, Ar, and CF₄ ;

and further comprising;

etching the TiO_y from the selected portions of outer regions of the sandwich regions with a solution of NH₄ OH or H₂ SO₄.

17. The method of processing a semiconductor wafer of claim 16 wherein the titanium is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.

18. The method of processing a semiconductor wafer of claim 16 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.

19. The method of processing a semiconductor wafer of claim 9 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates;

the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the TiO_y, the insulating dielectric deposited over the field effect transistor gates being selected such the TiO_y is selectively etchable relative to such insulating dielectric, and wherein the step of etching the TiO_y comprises etching the TiO_y with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.

20. A method of processing a semiconductor wafer comprising the following steps:

fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer;

converting the outwardly exposed surfaces of the active regions into a barrier transition metal silicide which connects with the active regions;

providing a layer of transition metal oxide over the barrier transition metal silicide of the active regions thereby producing sandwich regions of outer transition metal oxide regions and adjacent transition metal silicide in contact with the active regions;

the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer;

applying an insulating dielectric layer atop the wafer;

selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop in etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and

etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.

21. The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide are selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni, and W, or alloys thereof.

22. The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide comprises titanium.

23. The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the transition metal oxide comprises titanium.

24. The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide consists essentially of titanium.

25. The method of processing a semiconductor wafer of claim 20 wherein the step of converting comprises:

depositing a layer of transition metal atop the wafer over the outwardly exposed active region surfaces;

heating the wafer to react the transition metal over the outwardly exposed active regions with the underlying silicon to produce the transition metal silicide;

etching unreacted transition metal from the wafer;

and wherein the step of providing a layer of transition metal oxide over the barrier transition metal silicide comprises depositing a layer transition metal oxide.

26. The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide are selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof.

27. The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide comprises titanium.

28. The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the transition metal oxide comprises titanium.

29. The method processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide consists essentially of titanium.

30. The method of processing a semiconductor wafer of claim 20 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates;

the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the transition metal oxide, the insulating dielectric deposited over the field effect transistor gates being selected such the transition metal oxide is selectively etchable relative to such insulating dielectric, and wherein the step of etching the transition metal oxide comprises etching the transition metal oxide with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.

31. A method of processing a semiconductor wafer comprising the following steps:

fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer;

providing a layer of transition metal oxide elevationally above the active regions;

providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer;

applying an insulating dielectric layer elevationally above the transition metal oxide layer;

etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and

etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.

32. The method of processing a semiconductor wafer of claim 31 wherein the insulating dielectric barrier layer is provided to a thickness of at least 500 Angstroms.

33. The method of processing a semiconductor wafer of claim 31 wherein the barrier layer of insulating dielectric is provided to a thickness of at least 500 Angstroms;

and wherein,

the transition metal oxide is provided to a thickness of from about 200 Angstroms to about 4000 Angstroms.

34. A method of processing a semiconductor wafer comprising the following steps:

fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer;

providing a layer of transition metal oxide comprising a titanium oxide comprising a formula TiO_y, where "y" is from about 1.0 to 2.0 elevationally above the active regions;

providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer;

applying an insulating dielectric layer elevationally above the transition metal oxide layer;

etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and

etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.

35. The method of processing a semiconductor wafer of claim 34 wherein the insulating dielectric barrier layer is provided to a thickness of at least 500 Angstroms.

36. The method of processing a semiconductor wafer of claim 34 wherein the barrier layer of insulating dielectric is provided to a thickness of at least 500 Angstroms or greater;

and wherein,

the transition metal oxide is provided to a thickness of from about 200 Angstroms to about 4000 Angstroms.