Biomedical amplifier circuit

• US 5,206,602 A
• Filed: 04/30/1992
• Issued: 04/27/1993
• Est. Priority Date: 04/30/1992
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baumgartner, Richard A., Moore, Charles E.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US07/876,612
• Time in Patent Office: 362 Days
• Field of Search: 330/9, 330/252, 330/253, 330/257, 330/258, 330/260, 330/277
• US Class Current: 330/9
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: A61B 5/7242 using integration
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45775 by using cross switches
• CPC Class Codes: H03F 3/45941 Controlling the input circuit of the differential amplifier
• CPC Class Codes: H03F 3/45973 by using a feedback circuit
• CPC Class Codes: H03F 3/45995 using switching means

Abstract

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Claims

1. An electronic differential amplifier circuit comprising;

first stage amplifier means for receiving an input voltage and a gain feedback voltage and for generating a pair of first stage outputs by differentially amplifying said input voltage and said gain feedback voltage;

wherein said first stage amplifier means is chopper stabilized; and

second stage amplifier means for receiving said pair of first stage outputs and for generating a pair of second stage outputs by differentially amplifying said pair of first stage outputs;

wherein said pair of second stage outputs further comprise a negative gain second stage output and a positive gain second stage output; and

second stage common mode feedback means for receiving said pair of second stage outputs and for generating an average voltage by summing said pair of second stage outputs and for generating a second stage common mode feedback voltage by differentially amplifying said average voltage and a ground voltage;

wherein said second stage common mode feedback means is chopper stabilized; and

gain feedback means for receiving said negative gain second stage output and for generating said gain feedback voltage by forming a fraction of said negative gain second stage output.

2. An electronic differential amplifier circuit as in claim 1 wherein said first stage amplifier further comprises;

a first PMOS amplifier transistor having a gate connected to said input voltage, a source connected to a common bias current source, and a drain connected to a source of a first PMOS cascode transistor;

said first PMOS cascode transistor having a drain connected to a source of a second PMOS cascode transistor;

said second PMOS cascode transistor having a drain connected to a first output in said pair of first stage outputs and to a drain of a first NMOS cascode transistor;

said first NMOS cascode transistor having a source connected to a drain of a second NMOS cascode transistor;

said second NMOS cascode transistor having a source connected to a supply voltage; and

a second PMOS amplifier transistor having a gate connected to said gain feedback voltage, a source connected to said common bias current source, and a drain connected to a source of a third PMOS cascode transistor;

said third PMOS cascode transistor having a drain connected to a source of a fourth PMOS cascode transistor;

said fourth PMOS cascode transistor having a drain connected to a second output in said pair of first stage outputs and to a drain of a third NMOS cascode transistor;

said third NMOS cascode transistor having a source connected to a drain of a fourth NMOS cascode transistor;

said fourth NMOS cascode transistor having a source connected to said supply voltage.

3. An electronic differential amplifier circuit comprising:

first chopper means for receiving an input voltage and a gain feedback voltage and for generating a pair of first chopper outputs by chopping said input voltage and said gain feedback voltage; and

first stage signal amplifier means for receiving said pair of first chopper outputs and for generating a pair of first stage outputs by differentially amplifying said pair of first chipper outputs;

wherein said first stage signal amplifier means has a first stage common bias current; and

first stage common mode feedback amplifier means for receiving said pair of first stage outputs and a first reference voltage and for generating a first average by summing said pair of first stage outputs and for generating a first stage common mode bias feedback voltage by differentially amplifying said first average and said first reference voltage;

wherein said first stage common mode bias feedback voltage controls said first stage common bias current; and

second chopper means for receiving said pair of first stage outputs and for generating a pair of second chopper outputs by chopping said pair of first stage outputs;

wherein said second chopper means is synchronous with said first chopper means; and

second stage signal amplifier means for receiving said pair of second chopper outputs and for generating a pair of second stage outputs by differentially amplifying said pair of second chopper outputs;

wherein said pair of second stage outputs further comprise a negative gain second stage output and a positive gain second stage output; and

wherein said second stage signal amplifier means has a pair of variable output loads; and

third chopper means for receiving said second stage outputs and a ground voltage and for generating a second average by summing said pair of second stage outputs and for generating a pair of third chopper outputs by chopping said second average and said ground voltage; and

second stage common mode feedback amplifier means receiving said pair of third chopper outputs and for generating a pair of second stage common mode feedback voltages by differentially amplifying said pair of third chopper outputs; and

fourth chopper means for receiving said pair of second stage common mode feedback voltages and for generating a pair of fourth chopper outputs by chopping said pair of second stage common mode feedback voltages; and

current mirror means for receiving said pair of fourth chopper outputs and for converting said pair of fourth chopper outputs to a second stage load control voltage;

wherein said second stage load control voltage controls said pair of variable output loads; and

gain feedback means for receiving said negative gain second stage output and for generating said gain feedback voltage by forming a fraction of said negative gain second stage output.

4. An electronic differential amplifier circuit as in claim 3 wherein said first stage amplifier means further comprises;

a first PMOS amplifier transistor having a gate connected to a first output of said pair of first chopper outputs, a source connected to said first stage common bias current, and a drain connected to a source of a first PMOS cascode transistor;

said first PMOS cascode transistor having a drain connected to a source of a second PMOS cascode transistor;

said second PMOS cascode transistor having a drain connected to a first output in said pair of first stage outputs and to a drain of a first NMOS cascode transistor;

said first NMOS cascode transistor having a source connected to a drain of a second NMOS cascode transistor;

said second NMOS cascode transistor having a source connected to a supply voltage; and

a second PMOS amplifier transistor having a gate connected to a second output of said pair of first chopper outputs, a source connected to said first stage common bias current, and a drain connected to a source of a third PMOS cascode transistor;

said third PMOS cascode transistor having a drain connected to a source of a fourth PMOS cascode transistor;

said fourth PMOS cascode transistor having a drain connected to a second output in said pair of first stage outputs and to a drain of a third NMOS cascode transistor;

said third NMOS cascode transistor having a source connected to a drain of a fourth NMOS cascode transistor;

said fourth NMOS cascode transistor having a source connected to said supply voltage.

5. An electronic differential amplifier circuit as in claim 4 wherein said first stage common mode feedback amplifier means further comprises means for receiving said pair of first stage outputs and a first reference voltage and for generating a first average by summing said pair of first stage outputs and for generating a first stage common mode load feedback voltage by differentially amplifying said first average and said first reference voltage;

wherein said first stage common mode load feedback voltage is connected to a gate of said second NMOS cascode transistor and a gate of said fourth NMOS cascode transistor.

6. An electronic differential amplifier circuit comprising:

first and second input voltages; and

first and second input transistors, each having a source connected to a first supply voltage and a gate connected to said first input voltage; and

third and fourth input transistors, each having a source connected to said first supply voltage and a gate connected to said second input voltage; and

a first output voltage connected to a drain of said second input transistor and to a drain of a first variable load transistor and to a drain of a first common feedback transistor; and

a second output voltage connected to a drain of said fourth input transistor and to a drain of a second variable load transistor and to a drain of a second common feedback transistor; and

wherein a drain of said first input transistor is connected to a first input current source load and to a gate of said second variable load transistor; and

wherein a drain of said second input transistor is connected to a second input current source load and to a gate of said first variable load transistor; and

wherein a source of said first and second variable load transistors and said first and second common feedback transistors is connected to a second supply voltage; and

averaging means for receiving said first and second output voltages and for generating an average output voltage by summing said first and second output voltages; and

first chopper means for receiving said average voltage and a ground voltage and for generating first and second chopper outputs by chopping said average output voltage and said ground voltage; and

first feedback amplifier transistor having a source connected to a feedback amplifier common bias current source and a gate connected to said first chopper output; and

second feedback amplifier transistor having a source connected to said feedback amplifier common bias current source and a gate connected to said second chopper output; and

a first feedback output connected to a drain of said first feedback amplifier transistor and to a first feedback current source load and to a drain of a first feedback variable current source load and to a gate of a second feedback variable load; and

a second feedback output connected to a drain of said second feedback amplifier transistor and to a second feedback current source load and to a drain of said second feedback variable current source load and to a gate of said first feedback variable load; and

wherein a source of said first and second feedback variable current source loads is connected to said first supply voltage; and

second chopper means for receiving said first and second feedback outputs and for generating a pair of second chopper outputs by amplifying and chopping said first and second feedback outputs; and

current mirror means for receiving said pair of second chopper outputs and for generating a common feedback voltage from said pair of second chopper outputs;

wherein said common feedback voltage is connected to a gate of said first and second common feedback transistors.