Method and apparatus for multi-level tone display for liquid crystal apparatus

• US 5,206,635 A
• Filed: 01/30/1990
• Issued: 04/27/1993
• Est. Priority Date: 01/30/1989
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Video Engineering Incorporated
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Mano, Hiroyuki, Fujisawa, Kazuhiro, Inuzuka, Tatsuhiro, Konuma, Satoshi, Tsunekawa, Satoru, Kinugawa, Kiyoshige
• Primary Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/472,306
• Time in Patent Office: 1,183 Days
• Field of Search: 340/784, 340/793, 340/745, 340/750, 340/799, 358/236, 358/56, 358/59
• US Class Current: 345/99
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: H04N 3/127 using liquid crystals

Abstract

A liquid crystal display apparatus including a liquid crystal panel of a plurality of dots, an X drive circuit for supplying display information of at least one line to the liquid crystal panel and a Y drive circuit for selecting one-dot data for each line of the liquid crystal panel, the X drive circuit and the Y drive circuit enabling energization of the liquid crystal panel. A plurality of memories are provided for receiving a plurality of bits of information data and for storing at least M dot display information data so as to enable display of a respective line of the liquid crystal panel, M being an integer. A selection arrangement is provided for selecting one bit of display information data out of a plurality of bits of display information data to be read out of the memories and a selection controller is provided for specifying the one bit of display information data to be selected by the selection arrangement so as to enable read out of each one bit of the plurality of bits in a predetermined time sequence corresponding to one horizontal perioid divided by N for display, where N is an integer of at least two. The X drive circuit is supplied one dot information at leat two times during the one horizontal period so that one dot is controlled for display at least two times during the one horizontal period to enable multi-level tone display.

Claims

1. A liquid crystal display apparatus comprising a liquid crystal panel of a plurality of dots, Y drive circuit means for selecting a line of the liquid crystal panel, line memory means for storing bits of information data to be displayed, the line memory means having a capacity at least equal to the total number of bits of information data of one line of the liquid crystal panel, each dot of the line of the liquid crystal panel having two bits of display information, phase inverting circuit means for rearranging two-bit display information supplied from the line memory means in a one dot-wise manner in an X direction and in a one line-wise manner in a Y direction, the phase inverting circuit means rearranging the two-bit display information on a one-half horizontal scanning period timing basis, selecting means for selecting one-bit of the two-bit display information supplied from the phase inverting circuit means, and X drive circuit means for receiving the selected one-bit display information form the selecting means and for outputting a signal in a dot manner on a one-half of the horizontal scanning period interval timing basis for the liquid crystal panel, whereby a dot of the liquid crystal panel is displayed in accordance with outputs of the X drive circuit means and the Y drive circuit means.

2. A liquid crystal display apparatus according to claim 1, wherein the phase inverting circuit means inverts the phases of the predetermined two-bit display information.

3. A liquid crystal display apparatus according to claim 2, wherein the phase inverting circuit means inverts the phases of the predetermined two-bit display information so that the outputted signal by the X drive circuit means for one dot of the line of the liquid crystal panel has a predetermined relationship with respect to the signal for adjoining dots in the one line of the liquid crystal panel.

4. A liquid crystal display apparatus according to claim 2, wherein the phase inverting circuit means inverts the phases of the predetermined two-bit display information so that the output signal of the X drive circuit means for the one dot of the one line of the liquid crystal panel is a pulse having rising and falling portions at a timing opposite to a falling and rising portion of the adjoining dots in the one line of the liquid crystal display panel.

5. A liquid crystal display apparatus according to claim 1, wherein the phase inverting circuit means rearranges the two-bit display information so that the output signal of the X drive circuit means for one dot has rising and falling portions in opposition to the corresponding rising and falling portions of adjoining dots at the same timing.

6. A liquid crystal display apparatus according to claim 1, wherein the line memory means comprises a plurality of line memories.

7. A liquid crystal display apparatus comprising a liquid crystal panel of a plurality of dots, Y drive circuit means for selecting a line of the liquid crystal panel, line memory means for storing bits of information data to be displayed, the line memory means having a capacity at least equal to the total number of bits of information data of one line of the liquid crystal panel, each dot of the line of the liquid crystal panel having N bits of display information, wherein N is an integer of at least 2, data converting circuit means for converting the N-bit display information supplied from the line memory means to M-bit display information, wherein N is an integer and M≧

N, phase inverting circuit means for rearranging M-bit information supplied from the data converting circuit means in an M dot-wise manner in a X direction and in an M line-wise manner in a Y direction, the phase inverting circuit means rearranging the M-bit display information on a 1/M of a horizontal scanning period timing basis, selecting means for selecting one-bit of the M-bit display information of each dot, and X drive circuit means for receiving one-bit display information from the selecting means and for outputting a signal in a dot manner on a 1/M of the horizontal scanning period interval timing basis for the liquid crystal panel, whereby the liquid crystal panel displays a dot in accordance with outputs of the X drive circuit means and the Y drive circuit means.

8. A liquid crystal display apparatus according to claim 7, wherein the phase inverting circuit means inverts the phases of predetermined M-bit display information.

9. A liquid crystal display apparatus according to claim 7, wherein the phase inverting circuit means inverts the phases of the predetermined M-bit display information so that the outputted signal by the X drive circuit means for M dots of the line of the liquid crystal panel has a predetermined relationship with respect to the signal for adjoining dots in the one line of the liquid crystal panel.

10. A liquid crystal display apparatus according to claim 7, wherein the phase inverting circuit means inverts the phases of the predetermined M-bit display information so that the output signal of the X drive circuit means for the M dots of the one line of the liquid crystal panel is a pulse having rising and falling portions at a timing opposite to a falling and rising portion of adjoining dots in the one line of the liquid crystal display panel.

11. A liquid crystal display apparatus according to claim 7, wherein the phase inverting circuit means rearranges the M-bit display information so that the output signal of the X drive circuit means for M dots has rising and falling portions in opposition to the corresponding rising and falling portions of adjoining dots at the same timing.

12. A liquid crystal display apparatus according to claim 7, wherein the line memory means comprises a plurality of line memories.

13. A liquid crystal display apparatus according to claim 7, wherein N=2 and M=3.

14. A liquid crystal display apparatus according to claim 7, wherein N=3 and M=3.