Charge-controlled integrating successive-approximation analog-to-digital converter

• US 5,206,650 A
• Filed: 09/05/1991
• Issued: 04/27/1993
• Est. Priority Date: 09/05/1991
• Status: Expired due to Fees

• Current Assignee: John Fluke Mfg. Co., Inc.
• Original Assignee: John Fluke Mfg. Co., Inc.
• Inventors: Barr, A. Brinkley, Holmdahl, Todd E., Parle, Jonathan J.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): Young, Brian K.
• Application Number:
  US07/755,085
• Time in Patent Office: 600 Days
• Field of Search: 341/163, 341/127, 341/128, 341/129, 341/155, 341/164, 341/166, 341/167, 341/168, 341/169, 341/170, 341/159, 341/172
• US Class Current: 341/163
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14

Abstract

A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.

Claims

1. An analog-to-digital converter, comprising:

input means for receiving an analog voltage;

an integrator having an input coupled to said input means and an output, said integrator having a full-scale charge value dynamic operating range;

control means for controlling a state of charge of said integrator by causing said integrator to first store an acummulated charge proportional to said analog voltage, said accumulated charge being within said full-scale charge value dynamic operating range, and thereafter remove and add charge in a binary search sequence to determine digital bits representative of said analog voltage, said binary search sequence first locating the most significant bit by comparing said accumulated charge with one-half the full-scale charge value, and continuing through the search sequence to locate each successively less significant bit by comparing said accumulated charge with successively halved full-scale charge values; and

means coupled between the output of said integrator and said control means to monitor said state of charge and provide to said control means an indication of the logic states of said digital bits.

2. An analog-to-digital converter in accordance with claim 1 wherein said integrator comprises an operational amplifier having a capacitive element disposed between said input and said output, and said means coupled between the output of said integrator and said control means comprises a comparator having a first input coupled to said output of said integrator and a second input coupled to a reference level.

3. An analog-to-digital converter in accordance with claim 1 wherein said control means comprises means for generating predetermined currents for predetermined periods of time and causing said integrator to selectably integrate said currents.

4. An analog-to-digital converter in accordance with claim 3 wherein said control means includes timing means for establishing said predetermined periods of time, and said means for generating predetermined currents comprises at least one resistive element connectable between said input of said integrator and at least one predetermined reference voltage source.

5. An analog-to-digital converter in accordance with claim 4 wherein said means for generating predetermined currents comprises a plurality of resistors selectively connectable between said input of said integrator and predetermined positive and negative reference D.C. voltage sources.

6. An analog-to-digital converter in accordance with claim 5 wherein said plurality of resistors have binary-ratioed values.

7. An analog-to-digital converter in accordance with claim 5 wherein said plurality of resistors is a maximum of three having a binary-weighted relationship to each other.

8. An analog-to-digital converter, comprising:

an input voltage source providing an input voltage to be converted to a digital representation thereof;

an input network including at least one reference voltage source and a plurality of input resistors selectively connected to one of said input voltage source and said at least one reference voltage source;

an integrator having a full-scale charge value defining an operating range coupled to said input network, said integrator having a storage capacitor which when one of said plurality of input resistors is selectively connected to said input voltage source stores an accumulated charge proportional to said input voltage;

a comparator coupled to the output of said integrator for comparing the integrator output with a reference level and generating comparison signals in response thereto; and

control means including timing means coupled to the output of said comparator for controlling selection of said plurality of input resistors to provide said predetermined currents for predetermined periods of time to remove and add charge to said storage capacitor in a binary search sequence wherein the full-scale charge value is successively halved for each binary search, and producing in response to said comparison signals at the end of each binary search successively less significant digital bits representative of said input voltage.

9. An analog-to-digital converter in accordance with claim 8 wherein said plurality of input resistors have a binary-weighted relationship to each other.

10. An analog-to-digital converter in accordance with claim 8 wherein said timing means produces predetermined binary-related periods of time.