Method for arranging modules in an integrated circuit

• US 5,206,815 A
• Filed: 01/13/1989
• Issued: 04/27/1993
• Est. Priority Date: 01/13/1989
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Purcell, Shawn M.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/297,476
• Time in Patent Office: 1,565 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/119
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method for generating a layout of a rectangular block of cells for use with other rectangular blocks of cells in an integrated circuit. In the preferred embodiment, the method includes the steps of providing a set of component circuit cells, each of the cells being of generally rectangular shape with predefined dimensions and, then, concatenating the component cells with at least one expandable cell space between non-abutting adjacent edges of at least two of the elements such that the boundary of the concatenated set defines a block of cells having a generally rectangular shape which is coterminous with a second, predefined generally rectangular block of cells.

Claims

1. A method for generating a layout of a rectangular block of cells for use with a second rectangular block of cells in an integrated circuit, comprising the steps of:

a) providing a set of component circuit cells, each of the cells being of generally rectangular shape with predefined dimensions;

b) concatenating the component cells with at least one space cell that is expandable between non-abutting adjacent edges of at least two of the component cells such that the boundary of a concatenated set of component cells and at least one expandable space cell defines a block of cells having a rectangular shape which is coterminous and contiguous with said second rectangular block of cells.

2. A method according to claim 1, wherein:

said at least one of the expandable space cells includes wire routings having interconnection lines.

3. A method according to claim 2, including the step of specifying the location of at least one of the component cells.

4. An integrated circuit produced by a method comprising the steps of:

a) providing a set of component circuit cells, each of which has a generally rectangular shape with predefined dimensions;

b) concatenating the component cells with at least one space cell that is expandable between non-abutting adjacent edges of at least two of the component cells such that the boundary of a concatenated set of component cells and at least one expandable space cell defines a block of cells having a rectangular shape which is coterminous and contiguous with a second block of cells having the same rectangular shape.

5. An integrated circuit produced by a method according to claim 4, wherein;

said expandable space cells are comprised of white spaces and wire routing spaces including interconnection lines.

6. A method of generating an integrated circuit design layout, comprising the steps of:

providing at least one component circuit cell having a predefined layout;

designating at least one instance of the at least one cell in the integrated circuit design layout;

providing expandable space cells for insertion between adjacent instances of the component cells;

defining one or more slices, each slice comprised of at least one of said instances of the component cells;

defining a hierarchy for determining the positions of said instances of said cells in said integrated circuit design layout, including the steps of

a) resolving the positions of fixed instances of the cells;

b) resolving the positions of instances of said cells that are dependent on the positions of previously resolved instances; and

c) defining the dimensions of expandable space cells whereby contiguous slices are dimensionally equal in at least one dimension of width and height.

7. A method according to claim 6, including the step of defining the location of an instance by either fixing the relative position of the instance in said layout, making the position of the instance dependent on the position of another instance, or aligning the instance relative to at least one data port of another instance.