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Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus

  • US 5,206,830 A
  • Filed: 07/19/1991
  • Issued: 04/27/1993
  • Est. Priority Date: 07/06/1988
  • Status: Expired due to Term
First Claim
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1. A refresh control circuit for controlling a pseudo static random access memory cell, comprising:

  • control means for providing a memory request signal which alternatively changes between a selection level and a non selection level;

    a delay circuit for receiving said memory request signal, delaying said memory request signal by a predetermined delay time and outputting a delay memory request signal as a chip enable signal having a level change between a selection level and a non-selection level; and

    a refresh control signal output circuit for receiving said memory request signal and for outputting a refresh control signal, and said refresh control signal output circuit responding to the level change of said memory request signal between said selection level and said non-selection level for changing said refresh control signal for ma first level to a second level at a first predetermined time lapse after said level change of said memory request signal between said selection level and said non-selection level has occurred nd thereafter changing said refresh control signal from said second level to said first level at a second predetermined time lapse, andwherein said level of said refresh control signal changes from si second level to said first level after said level of said chip enable signal changes between said selection level said non-selection level, said pseudo static random access memory cell changes to write mode when said chip enable signal take said selection level, said refresh control signal takes said selection level, said refresh control signal takes said first level and said signal is outputted from said control means, said refresh control signal changing to a read mode when said chip enable signal takes said selection level, said refresh control signal takes first level and said write signal is prevented from being outputted from said control means, and changes to a refresh mode when said chip enable signal takes said non-selection level and said refresh control signal further takes said second level whether or not said write signal is being outputted from said control means.

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