Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus

• US 5,206,830 A
• Filed: 07/19/1991
• Issued: 04/27/1993
• Est. Priority Date: 07/06/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ueno, Hisashi, Isobe, Mitsuo
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/733,126
• Time in Patent Office: 648 Days
• Field of Search: 365/194, 365/222, 365/233, 307/592, 307/596, 307/601, 307/602, 307/606
• US Class Current: 365/194
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs

Abstract

A refresh control circuit for a pseudo static random access memory includes a refresh control signal output circuit for outputting a refresh control signal to accomplish refresh control of the pseudo static random access memory, and includes a delay circuit. A first chip enable signal from a control device such as a MPU is delayed by the delay circuit and outputted as a second chip enable signal for the PSRAM. As the first chip enable signal level changes from a selection level to a non-selection level, the refresh control signal level changes to a non-refresh level. This state is maintained for a predetermined period. After the second chip enable signal changes from the selection level to the non-selection level, the refresh control signal returns from the non-refresh level to the refresh level. Thus, the PSRAM enters into the refresh state during the non-selection state, and is refreshed. This refresh operation is necessarily performed after an access to PSRAM.

Claims

1. A refresh control circuit for controlling a pseudo static random access memory cell, comprising:

control means for providing a memory request signal which alternatively changes between a selection level and a non selection level;

a delay circuit for receiving said memory request signal, delaying said memory request signal by a predetermined delay time and outputting a delay memory request signal as a chip enable signal having a level change between a selection level and a non-selection level; and

a refresh control signal output circuit for receiving said memory request signal and for outputting a refresh control signal, and said refresh control signal output circuit responding to the level change of said memory request signal between said selection level and said non-selection level for changing said refresh control signal for ma first level to a second level at a first predetermined time lapse after said level change of said memory request signal between said selection level and said non-selection level has occurred nd thereafter changing said refresh control signal from said second level to said first level at a second predetermined time lapse, and

wherein said level of said refresh control signal changes from si second level to said first level after said level of said chip enable signal changes between said selection level said non-selection level, said pseudo static random access memory cell changes to write mode when said chip enable signal take said selection level, said refresh control signal takes said selection level, said refresh control signal takes said first level and said signal is outputted from said control means, said refresh control signal changing to a read mode when said chip enable signal takes said selection level, said refresh control signal takes first level and said write signal is prevented from being outputted from said control means, and changes to a refresh mode when said chip enable signal takes said non-selection level and said refresh control signal further takes said second level whether or not said write signal is being outputted from said control means.

3. A refresh control circuit according to claim 1, wherein said refresh control signal output circuit and said delay circuit are coupled in parallel for receiving said memory request signal.

4. A refresh control circuit according to claim 3, wherein,

said refresh control signal output circuit comprises a first serial circuit including, in order, a first inverter, a first RC delay circuit, a second inverter, a second RC delay circuit, a third inverter and an exclusive NOR circuit and

said delay circuit comprises a second serial circuit including, in order, a first inverter, an RC delay circuit and a second inverter.

5. A refresh control circuit according to claim 1, wherein said refresh control signal output circuit includes said delay circuit.

6. A refresh control circuit according to claim 5, wherein,

said refresh control signal output circuit comprises a first serial circuit including, in order, a first inverter, a first RC delay circuit, a second inverter, a second RC delay circuit, a third inverter and an exclusive NOR circuit and

said delay circuit comprises a second serial circuit including said first inverter, said first RC delay circuit and said second inverter of said refresh control signal output circuit.

2. A pseudo static random access memory apparatus, comprising:

a control device;

only one pseudo static random access memory cell;

an address bus, a data bus and a write signal line each respectively coupling said control device to said pseudo static random access memory cell;

a refresh control circuit;

a memory request signal lien coupling said control deice to said refresh control circuit; and

a chip enable signal line and a refresh control signal line, each respectively coupling said refresh control circuit to said pseudo static random access memory cell,

wherein said control deice supplies a memory request signal, having levels which alternatively change between a selection level and a non-selection level, to said refresh control circuit, supplying an address signal, which designates at least one memory cell in said pseudo static random access memory, to said pseudo static random access memory cell and supplying a write signal for changing an operating mode of said pseudo static random access memory cell to a write mode to said pseudo static random access memory cell, and

said refresh control circuit comprising;

a delay circuit for delaying said memory request signal by a predetermined time delay to produce a delayed memory request signal and for supplying said delayed memory request signal to said pseudo static random access memory cell as a chip enable signal, said chip enable signal having a level change between a selection level and a non-selection level, and

a refresh control signal output circuit for supplying a refresh control signal to said pseudo static random access memory cell,

said refresh control signal output circuit changing levels of said refresh control signal on the basis of level changing of said memory request signal changing between said selection level and said non-selection level,

said refresh control signal output circuit changing said refresh control signal from a first level to a second level at a predetermined time lapse after said memory request signal changes between said selection level and said non-selection level, and

thereafter said refresh control signal output circuit changing said refresh control signal from said second level to said first level after level changing of said chip enable signal between said selection level and said non-selection level,

said pseudo static random access memory cell changing to a write mode when said chip enable signal takes said selectional level, said refresh control signal takes said first level and said write signal is outputted from said control device, changing to a read more when said chip enable signal takes said selection level, said refresh control signal takes said first level and said write signal is not outputted from said control device, and changing to a refresh mode when said chip enable signal takes said non-selection level and said refresh control signal takes said second level whether or not said write signal is being outputted from said control device.

7. A pseudo static random access memory apparatus according to claim 2, wherein said refresh control signal output circuit and said delay circuit have respective inputs coupled in parallel to receive said memory request signal.

8. A pseudo static random access memory apparatus according to claim 7, wherein said refresh control signal put circuit comprise a first serial circuit including, in order, a first inverter, a first RC delay circuit, a second inverter, a second RC delay circuit, a third inverter and an exclusive NOR circuit and

said delay circuit comprises a second serial circuit including, in order, a first inverter, an RC delay circuit and a second inverter.

9. A pseudo static random access memory apparatus according to claim, wherein said refresh control signal output circuit includes said delay circuit.

10. A pseudo static random access memory apparatus according to claim 9, wherein

said refresh control signal output circuit comprises a first serial circuit including, in order, a first inverter, a first RC delay circuit, a second inverter, a second RC delay circuit, a third inverter and an exclusive NOR circuit and

said delay circuit comprise a second serial circuit including said first inverter, said first RC delay circuit and said second inverter of said refresh control signal output circuit.