Serial access semiconductor memory device having a redundancy system

• US 5,206,831 A
• Filed: 11/30/1990
• Issued: 04/27/1993
• Est. Priority Date: 11/30/1989
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Wakamatsu, Masataka
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/620,080
• Time in Patent Office: 879 Days
• Field of Search: 365/200, 365/230.08, 365/189.07, 371/10.2, 371/10.3
• US Class Current: 365/200
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 29/86 in serial access memories, e.g. shift registers, CCDs, bubble memories

Abstract

A serial access semiconductor memory device having a column redundant system employs a parallel-serial conversion circuit including a plurality of series connected flipflop circuits and a plurality of selectors provided between the flipflop circuit. At the selector associated unit the final stage of the flipflop circuits in the parallel-serial conversion circuit, defective data from a memory cell array are replaced to redundant data from the column redundant system without large scale circuitry and complicated control signals. An improved fuse ROM or an improved comparator is employed for the semiconductor memory device to control the switching from the defective data to redundant data. The fuse ROM employs a latch circuit for reducing stand-by current. The comparator employs a plurality of MOS transistors to compare effectively. The relation between the fuse ROM and the comparator provides a simplified circuit construction of an asynchronous multi-port device or a device having a plurality of memory blocks.

Claims

1. A semiconductor memory device for reading out serial data stored therein, comprising:

a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns,

column redundancy means for storing data in lieu of a defective memory cell of the array, being located adjacent the array, having a plurality of memory cells in which the number of rows of the memory cells therein is equal to that of the array,

selecting means for selecting one of the rows of the array and the column redundancy means simultaneously to output data from the array and the column redundancy means in parallel in responsive to a readout address signal,

controlling means for generating a switching control signal by comparing a defective address signal with the readout address signal,

parallel-serial converting means for inputting the data from the array and the column redundancy means and for outputting the data in series, comprising;

a plurality of flip-flop circuits connected in series, in which the final stage of the flip-flop circuits outputs the data in series,

a plurality of selectors for selecting data from the array and from the flip-flop circuit, being provided between the flip-flop circuits, wherein one of the selectors which is associated with the final stage selects the data from the column redundancy means and the data from the array or the flip-flop circuit in responsive to the switching control signal.

2. A semiconductor memory device according to claim 1, wherein the controlling means includes a fuse read only memory in which the defective address signal according to the defective memory cell is stored, and comparing means for comparing the defective address signal from the fuse read only memory with the readout address signal.

3. A semiconductor memory device according to claim 2, wherein the comparator comprising:

a plurality of sets of a pair of MOS transistor, the sets being connected in parallel between a first potential and second potential, one of MOS transistor of a pair being controlled by the defective address signal or a complemental defective address signal, the other of MOS transistor of a pair being controlled by the readout address signal or a complemental readout address signal, the number of the sets being equal to the twice of the bit number of the address signals.

4. A semiconductor memory device according to claim 3, wherein the MOS transistors controlled by the defective address signal or the complemental defective address signal are connected to a node which is connected to the first potential via a pre-charge transistor pre-charging the node to the first potential, and wherein the switching control signal reflects a level of the node.

5. A semiconductor memory device according to claim 2, wherein the parallel-serial converting means consists of a plurality of parallel-serial converters operating asynchronously, and wherein the comparing means consists of a plurality of comparators comparing the defective address signal from the fuse read only memory with the readout address signals generated asychronously from a plurality of column counters.

6. A semiconductor memory device according to claim 2, wherein the array of the memory cells is divided into a plurality of memory blocks, and wherein the controlling means includes a plurality of fuse read only memories each corresponding to the respective memory blocks.

7. A semiconductor memory device according to claim 2, wherein the fuse read only memory comprises at least a cell storing a data of 1 bit, the cell including a fuse and a MOS transistor which are connected in series between a first potential and a second potential, the gate of the MOS transistor being supplied with a level which is an inverted level of the node between the fuse and the MOS transistor.

8. A semiconductor memory device according to claim 7, wherein the level which is supplied to the gate is produced by a inverter having a complementary MOS transistor structure.

9. A semiconductor memory device according to claim 1, further comprising the column redundancy means having a plurality of columns of memory cell, a redundant data buffer for storing parallel data from the column redundancy means, and a redundant selector for selecting the data from the parallel data of the redundant data buffer in corresponding to a signal from the controlling means to output to the selector being associated with the final stage.

10. A semiconductor memory device comprising,

a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns,

column redundancy means for storing data in lieu of a defective memory cell of the array, being located adjacent the array, having a plurality of columns of memory cells,

selecting means for selecting one of the rows of the array and the column redundancy means simultaneously to output data from the array and the column redundancy means in parallel in responsive to a readout address signal,

a data buffer for storing parallel data from the array,

a redundant data buffer for storing parallel data from the column redundancy means,

a read only memory in which the defective address signal according to the defective memory cell is stored,

comparing means for comparing the defective memory address signal from the read only memory with the readout address signal, and generating a switching control signal and a redundant selector control signal,

parallel-serial converting means for inputting the data from the data buffer and the redundant data buffer and for outputting the data in series, comprising;

a plurality of flip-flop circuits connected in series, in which the final stage of the flip-flop circuits outputs the data in series, and a plurality of selectors for selecting data from the array and from the flip-flop circuits, being provided between the flip-flop circuits, wherein one of the selectors which is associated with the final stage selects the data from the column redundancy means, the data from the array and the data from the flip-flop circuits in responsive to the switching control signal, and

a redundant selector for selecting the data from the parallel data of the redundant buffer corresponding to the redundant selector control signal to output to the selector being associated with the final stage.