Electronic phase shifting circuit for use in a phased radar antenna array
First Claim
1. A phase bit circuit for receiving an input signal and producing an output signal which is selectively shifted in phase by a first predetermined amount or a second predetermined amount relative to the input signal, comprising;
- input terminal means for inputting the input signal;
output terminal means for outputting the output signal;
first transmission line means coupled between the input and output terminal means;
a first diode coupled between the first transmission line means and the input terminal means;
a second diode coupled between the first transmission line means and the output terminal means;
second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween;
a third diode coupled between said junction of the second and third transmission line means and ground; and
biasing means coupled to the first, second and third diodes for selectively forward biasing the first, second and third diodes to cause substantially all of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means to constitute the output signal which is shifted in phase relative to the input signal by the first predetermined amount;
or reverse biasing the first, second and third diodes to cause a first portion of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means and a second portion of the input signal to propagate from the input terminal means through the second and third transmission line means to the output terminal means, said first and second portions of the input signal combining at the output terminal means to constitute the output signal which is phase shifted in phase relative to the input signal by the second predetermined amount.
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Accused Products
Abstract
A phase shifting circuit (10) which is especially suitable for use as a 180° phase bit for an antenna element in a phased radar antenna array includes a first transmission line (16) connected between first and second diodes (22,24), which are connected to input and output terminals (12,14) respectively. Second and third transmission lines (18,20) are connected in series with each other between the input and output terminals (12,14). A third diode (26) is connected between the junction (28) of the second and third transmission lines (18,20) and ground. The first transmission line (16) is less than one-quarter wavelength long at the operating frequency of the circuit (10), whereas the second and third transmission lines (18,20) are each approximately three-eighths wavelength long. Forward biasing the diodes (22,24,26) causes substantially all of the signal to propagate from the input terminal (12) to the output terminal (14) through the first transmission line (16), producing minimum phase shift. Reverse biasing the diodes (22,24,26) causes a major portion of the signal to propagate through the second and third transmission lines (18,20), producing maximum phase shift.
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Citations
20 Claims
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1. A phase bit circuit for receiving an input signal and producing an output signal which is selectively shifted in phase by a first predetermined amount or a second predetermined amount relative to the input signal, comprising;
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input terminal means for inputting the input signal; output terminal means for outputting the output signal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and biasing means coupled to the first, second and third diodes for selectively forward biasing the first, second and third diodes to cause substantially all of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means to constitute the output signal which is shifted in phase relative to the input signal by the first predetermined amount;
or reverse biasing the first, second and third diodes to cause a first portion of the input signal to propagate from the input terminal means through the first transmission line means to the output terminal means and a second portion of the input signal to propagate from the input terminal means through the second and third transmission line means to the output terminal means, said first and second portions of the input signal combining at the output terminal means to constitute the output signal which is phase shifted in phase relative to the input signal by the second predetermined amount. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A phase bit circuit, comprising:
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an input terminal; an output terminal; first transmission line means coupled between the input and output terminal means; a first diode coupled between the first transmission line means and the input terminal means; a second diode coupled between the first transmission line means and the output terminal means; second and third transmission line means connected in series with each other between the input and output terminal means, the second and third transmission line means defining a junction therebetween; a third diode coupled between said junction of the second and third transmission line means and ground; and circuit means coupled to the first, second and third diodes for selectively applying a first bias voltage for forward biasing the first, second and third diodes;
or a second bias voltage for reverse biasing the first, second and third diodes. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification