Method and structure for decoding Huffman codes using leading ones detection

• US 5,208,593 A
• Filed: 06/26/1992
• Issued: 05/04/1993
• Est. Priority Date: 07/30/1991
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Tong, Po, Ruetz, Peter A.
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US07/905,257
• Time in Patent Office: 312 Days
• Field of Search: 341/65, 341/67, 341/95
• US Class Current: 341/65
• CPC Class Codes: H03M 7/425 for the decoding process only

Abstract

A method and a structure are provided for decoding Huffman codes using a random access memory having a size less than twice the total number of codewords decodable. Under this method, the number of leading 1'"'"'s in a Huffman codeword and the bits of the Huftman code word other than the leading 1'"'"'s ("remainder") are combined to form an address into the random access memory. Using the fact that, for a given number of leading 1'"'"'s in a Huffman code, the possible remainder of the Huffman code is no longer than a predetermined number of bits, the size of the random access memory necessary for decoding such Huffman codes can be made optimally small.

Claims

1. A method for decoding a variable length codeword embedded in a bit stream, comprising the steps of:

detecting the number of leading 1'"'"'s in said variable length codeword;

looking up from a first storage means (i) a "tail length" corresponding to the maximum number of bits following said number of leading 1'"'"'s in said variable length codeword; and

(ii) a first memory address;

separating from said bit stream in accordance with said tail length a bit string including the bits of said codeword following said leading 1'"'"'s;

combining said first memory address and said bit string to form a second memory address; and

using said second address to access a second storage means to obtain a decoded value of said codeword.

2. A method as in claim 1, wherein said step of separating further comprises the steps of:

providing said bit string in a reversed order from the order the bits in said bit string are provided in said bit stream; and

setting to zero in said bit string all bits not belonging to said codeword.

3. A method as in claim 2, wherein said step of combining comprises the step of adding said first memory address to said bit string.

4. A method as in claim 1, wherein said method further comprises, prior to said detecting step, the step of aligning in said bit stream said variable code by shifting out a variable code previously decoded.

5. A method as claim 1, wherein said second memory address selects a location in said second storage means from a number of memory locations no more than 2K- log₂ K -1, where K is the number of all possible decoded values.

6. A method as in claim 1, wherein, when at least one bit follows said leading 1'"'"'s in said codeword, a `0` bit follows in said codeword said leading 1'"'"'s, and wherein said bit string does not include said `0` bit.

7. A structure for decoding a variable length codeword embedded in a bit stream, comprising:

means for detecting the number of leading 1'"'"'s in said variable length codeword;

means for looking up from a first storage means (i) a "tail length" corresponding to the maximum number of bits following said number of leading 1'"'"'s in said variable length codeword; and

(ii) a first memory address;

means for separating from said bit stream in accordance with said tail length a bit string including the bits of said codeword following said leading 1'"'"'s;

means for combining said first memory address and said bit string to form a second memory address; and

means, using said second address, for accessing a second storage means to obtain a decoded value of said codeword.

8. A structure as in claim 7, wherein said means for separating further comprises:

means for providing said bit string in a reversed order from the order the bits in said bit string are provided in said bit stream; and

means for setting to zero in said bit string all bits not belonging to said codeword.

9. A structure as in claim 8, wherein said means for combining comprises means for adding said first memory address to said bit string.

10. A structure as in claim 7, wherein said structure further comprises means for aligning in said bit stream said variable code by shifting out a variable code previously decoded.

11. A structure as claim 7, wherein said second memory address selects a location of said second storage means from a number of memory locations no more than 2K- log₂ K -1, where K is the number of all possible decoded values.

12. A structure as in claim 7, wherein, when at least one bit follows said leading 1'"'"'s in said codeword, a `0` bit follows in said codeword said leading 1'"'"'s, and wherein said bit string does not include said `0` bit.