Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof

• US 5,208,778 A
• Filed: 07/30/1991
• Issued: 05/04/1993
• Est. Priority Date: 11/16/1988
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Inoue, Yoshinori, Komatsu, Takahiro, Konishi, Yasuhiro, Dosaka, Katsumi, Kumanoya, Masaki
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US07/739,736
• Time in Patent Office: 644 Days
• Field of Search: 365/51, 365/63, 365/200, 365/201, 371/10.1, 371/10.2, 371/10.3, 371/21.1, 371/21.2
• US Class Current: 365/201
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

Claims

1. A dynamic-type semiconductor memory device including a memory cell array having a plurality of memory cells, each of said cells storing information therein, and operable in a test mode operation for simultaneously selecting a prescribed number of the memory cells in said memory cell array, simultaneously writing information in said prescribed number of memory cells selected, and then simultaneously reading information stored in said prescribed number of memory cells, and determining acceptability of said semiconductor memory device according to the information read out, said device comprising:

generating means for generating an internal test mode signal designating said test mode,

selecting means activated in response to said test mode signal for simultaneously selecting said prescribed number of memory cells from said memory cell array in accordance with an address externally provided,

receiving means for receiving write-in data externally applied,

writing means coupled to said receiving means for writing a data value inverted from the value of said write-in data in at least one but not all memory cells of said prescribed number of memory cells selected, and also writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said selected prescribed number of selected memory cells,

accessing means for accessing said selected prescribed number of selected memory cells, said accessing means including reading means for inverting and reading the stored data value of said at least one memory cell where said inverted data value is written, and reading the stored data values of said remaining memory cells as they are, and

logic means activated in response to said test mode signal for receiving all of the output data from said reading means and outputting a logic value corresponding to the data received, wherein

said memory cell array comprises a plurality of bit line pairs, each of said plurality of bit line pairs having a first bit line to which a data value of a selected memory cell is transmitted, and a second bit line to which a data value complementary to the data value on said first bit line is transmitted,

said writing means and said reading means comprise a plurality of internal data transmitting line pairs, the number of said plurality of internal data transmitting line pairs corresponding to the number of memory cells selected simultaneously, and connecting means for connecting each internal data transmitting line pair with corresponding bit line pairs, connection of the bit line pairs of accessed memory cells to at least one but not all internal data transmitting line pairs being the reverse of the connection of the bit line pairs of corresponding accessed memory cells to the remaining internal data transmitting line pairs.

2. A method of performing a functional testing of a dynamic-type semiconductor memory device comprising a memory cell array having a plurality of memory cells each storing information, the plurality of memory cells connected to a plurality of internal data transmitting line pairs through corresponding bit line pairs, the connection of the bit line pairs of corresponding memory cells to at least one internal data transmitting line pair being the reverse of the connection of the bit line pairs of corresponding memory cells to remaining internal data transmitting line pairs, said method comprising the steps of:

generating a test mode signal designating a functional test mode,

simultaneously selecting from said memory cell array, a prescribed number of memory cells corresponding to an address externally applied,

receiving external write-in data values,

writing a data value inverted from the corresponding data value of said write-in data in at least one but not all of said prescribed number of memory cells selected, and writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said prescribed number of memory cells selected, in response to said test mode signal,

accessing said prescribed number of memory cells selected, inverting and reading stored data of at least one memory cell in which said inverted data is written, and reading the stored data values of said remaining memory cells in non-inverted form, and

outputting a logic value corresponding to the stored data read from said prescribed number of memory cells in response to a test mode instructing signal.

3. A method of performing a function testing of a dynamic-type semiconductor memory device in accordance with claim 2, wherein said memory cell array is divided into a plurality of subarray blocks, and said simultaneously selecting step includes a step of selecting a 1-bit memory cell from each of said subarray blocks.

4. A method in accordance with claim 2, wherein said outputting step includes the step of determining whether or not read-out data are the same as each other.

5. A dynamic-type semiconductor memory device including a plurality of memory cells arranged in a matrix of rows and columns

means for selecting simultaneously a predetermined number of memory cells, in response to an externally applied address;

a plurality of complementary internal data transmission line pairs for transferring data to be written or to be read, said plurality of complementary internal data transmission line pairs being related in number to the number of simultaneously injected memory cells; and

connecting means for connecting complementary bit line pairs of the predetermined number of simultaneously selected memory cells with respective complementary internal data transmission line pairs in response to said externally applied address, wherein

the connection between the complementary bit line pair of at least one selected memory cell and the corresponding complementary internal data transmission line pair is the reverse of the connections between the complementary bit line pairs and pairs for the remaining selected memory cells.

6. A connection arrangement facilitating testing of a memory having a plurality of memory cells and in which during at least testing of said memory cells a group of memory cells are accessed as a unit for writing of data and accessed as a unit for reading of said group of cells comprising:

a plurality of internal data transmitting line pairs, said internal data transmitting line pairs corresponding to the number of memory cells of said group, and connecting means for connecting each of said internal data transmitting line pairs with each of a plurality of bit line pairs, wherein

input connections from an internal data transmitting line pair to a corresponding bit line pair of at least one cell of said group of memory cells are the reverse of the input connections between the internal data transmitting line pairs and the corresponding bit line pairs of the remaining memory cells of said group to complement a corresponding at least one bit of said data written into said group of cells and

output connections from said internal data transmitting line pair to said corresponding bit line pair of said at least one cell of said group of memory cells are correspondingly the reverse of the output connections between said internal data transmitting line pairs and said corresponding bit line pairs of the remaining memory cells of said group to complement said corresponding at least one bit of data read from said group of cells.

7. A connection arrangement as recited in claim 6, wherein a set of input/output lines are used for both input and output of data to said memory cells and said reversed input connection and said reversed output connections comprise a single reversed connection of said set of input/output lines to a cell of said group of memory cells.

8. A connection arrangement as recited in claim 6, wherein during testing, test data of a common logic state is written into all memory cells of said group.

9. A dynamic-type semiconductor memory device comprising a plurality of memory cell arrays each including memory cells arranged in a matrix of rows and columns;

each of said memory cell arrays comprising sets of bit lines for connecting memory cells of said columns to corresponding sense amplifiers;

a plurality of input and output data transmission line pairs for transferring data to be written or to be read, the number of said plurality of input and output data transmission line pairs corresponding to the number of memory cell arrays;

means for selecting simultaneously a number of memory cells in each memory cell array corresponding to the number of said plurality of input and output data transmission line pairs, in response to an externally applied address; and

connecting means for connecting the simultaneously selected memory cells, through respective bit lines and sense amplifiers, with respective ones of said plurality of input and output data transmission line pairs in predetermined relationships;

wherein the connection between the bit lines and the input and output data transmission line pairs of at least one, but not all of the memory cell arrays, is the reverse of the connections between the bit lines and the input and output data transmission line pairs for the remaining memory cells arrays.

10. A dynamic-type semiconductor memory device as recited in claim 9 further comprising

generating means for generating a test mode designating signal;

test write-in data means, responsive to said test mode designating signal, for simultaneously applying test mode data to said data transmission lines, wherein inverted write-in data are stored in the selected memory cells of said at least one memory cell array having the reverse connection and non-inverted write-in data are stored in the selected memory cells of the remaining memory cell arrays having non-reverse connections;

accessing means for simultaneously accessing and reading said selected memory cells, wherein the data stored in the selected cells of the memory cell arrays having reversed connection relationship are inverted and applied to corresponding data transmission lines and the stored data of the selected memory cells in said remaining memory cells arrays are applied in non-inverted form to corresponding data transmission lines; and

logic means activated in response to said test mode designating signal for receiving all of the data from said data transmission lines and outputting a logic value corresponding to the data received.

11. A dynamic-type semiconductor memory device including a plurality of memory array blocks, each of said memory array blocks including a plurality of memory cells each of which cell stores information therein, and operable in a test mode operation for simultaneously selecting a predetermined number of memory cells from said plurality of memory array blocks, simultaneously writing information in said predetermined number of memory cells selected, and then simultaneously reading information stored in said predetermined number of memory cells, and estimating reliability of said memory device according to the information read out, said device comprising:

generating means for generating an internal test mode signal designating said test mode;

selecting means activated in response to said internal test mode signal for simultaneously selecting said predetermined number of memory cells from said memory array blocks in accordance with a received address, wherein at least one memory cells is selected in each memory array block;

receiving means for receiving write-in data values externally applied;

writing means coupled to said receiving means for writing a data value inverted from the corresponding data value of said write-in data in at least one but not all memory cells of said predetermined number of memory cells simultaneously selected, and also simultaneously writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said predetermined number of memory cells simultaneously selected;

accessing means for accessing said predetermined number of memory cells simultaneously selected, said accessing means including reading means for inverting and reading the stored data of said at least one memory cell where said inverted data is written, and simultaneously reading the stored data of said remaining memory cells as they are; and

logic means activated in response to said internal test mode signal for receiving all of the output data from said reading means and outputting a logic value corresponding to the data received.

12. A dynamic-type semiconductor memory device as recited in claim 11, wherein the memory cells simultaneously selected from said plurality of memory cell arrays have row and column addresses corresponding to each other.

13. A dynamic-type semiconductor memory device including a plurality of memory array blocks, each of said memory array blocks including a plurality of memory cells each of which cells storing information therein, and operable in a test mode operation for simultaneously selecting a predetermined number of memory cells from said plurality of memory array blocks, simultaneously writing information in said predetermined number of memory cells selected, and then simultaneously reading information stored in said predetermined number of memory cells, and estimating reliability of said memory device according to the information read out, said device comprising:

generating means for generating an internal test mode signal designating said test mode;

selecting means activated in response to said internal test mode signal for simultaneously selecting said predetermined number of memory cells from said memory array blocks in accordance with a received address, wherein at least one memory cells is selected in each memory array block;

receiving means for receiving write-in data values externally applied;

writing means coupled to said receiving means for writing a data value inverted from the corresponding data value of said write-in data in at least one but not all memory cells of said predetermined number of memory cells simultaneously selected, and also simultaneously writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said predetermined number of memory cells simultaneously selected;

accessing means for accessing said predetermined number of memory cells simultaneously selected, said accessing means including reading means for inverting and reading the stored data of said at least one memory cell where said inverted data is written, and simultaneously reading the stored data of said remaining memory cells as they are; and

logic means activated in response to said internal test mode signal for receiving all of the output data from said reading means and outputting a logic value corresponding to the data received, wherein

each said memory array block comprises a plurality of bit line pairs, each bit line pair having a first bit line to which data of a memory cell is transmitted, and a second bit line to which data complementary to the data on said first bit line is transmitted, and

said writing means and reading means each comprise a plurality of internal data transmitting line pairs, said internal data transmitting line pairs corresponding in number to memory cells selected simultaneously, and connecting means for connecting each of said internal data transmitting line pairs with each of said predetermined number of memory cells simultaneously selected through associated bit line pairs, connection of at least one bit line pair associated with said at least one selected memory cell to the related internal data transmitting line pair being the reverse of the connections of the bit line pairs associated with each of said remaining selected memory cells to the related internal data transmitting line pairs.

14. A method of performing a functional testing of a dynamic-type semiconductor memory device comprising a plurality of memory array blocks each including a plurality of memory cell, each of said memory cells stores information therein, comprising the steps of:

generating a test mode signal designating a functional test mode;

simultaneously selecting from each of said memory array blocks a predetermined number of memory cells corresponding to a received address;

receiving write-in data externally applied;

writing a data value inverted from the corresponding data value of said write-in data in at least one but not all memory cells of said predetermined number of memory cells, and writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said predetermined number of memory cells, in response to said test mode signal;

accessing said predetermined number of memory cells simultaneously selected, inverting and reading stored data of said at least one memory cell in which said data inverted is written, and reading the stored data of said remaining memory cells of said predetermined number of memory cells in noninverted form; and

output a logic value corresponding to the data read from said predetermined number of memory cells in response to said test mode signal.

15. A dynamic type memory device comprising:

a plurality of memory cells each for storing information;

test mode signal generating means for generating a test mode designating signal designating a test mode;

selection means receiving said test mode designating signal from said test mode signal generating means and for selecting simultaneously a predetermined number of memory cells from said plurality of memory cells according to an address signal when said test mode signal designates said test mode;

writing means for receiving external data and for writing a data value inverted from the corresponding data value of said external data inputted into at least one memory cell among said predetermined number of memory cells selected by said selecting means, and also writing data values having the same corresponding values as that of said external data inputted into at least one of the remaining memory cells of said predetermined number of memory cells selected by said selecting means, in the test mode;

reading means for reading out the data of a memory cell storing the data inverted from the value of said external data inputted, and inverting the read-out data to be output, and also for reading out the data of a memory cell storing data with the same value as said external data inputted to be output, in the test mode; and

logic operation means for receiving the data outputted from said reading means to provide a logic value corresponding to the data received from said reading means.

16. A memory device according to claim 15, wherein

said plurality memory cells are arranged in a memory cell array, and said memory cell array comprises a plurality of bit line pairs, each of said plurality of bit line pairs having a first bit line to which data of a selected memory cell are transmitted, and a second bit line to which data complementary to the data on said first bit line are transmitted,

said writing means and said reading means comprise a plurality of internal data transmitting line pairs, the number of said plurality of internal data transmitting line pairs corresponding to the number of memory cells selected simultaneously, and connecting means for connecting each internal data transmitting line pair with corresponding bit line pairs, connection of the bit line pairs accessed memory cells to at least one but not all internal data transmitting line pairs being the reverse of the connection of the bit line pairs of corresponding accessed memory cells to the remaining internal data transmitting line pairs.

17. A method of performing a functional testing of a dynamic-type semiconductor memory device comprising a plurality of memory array blocks each including a plurality of memory cells each storing information therein, comprising the steps of:

generating a test mode signal designating a functional test mode;

simultaneously selecting from each of said memory array blocks a predetermined number of memory cells corresponding to a received address;

receiving write-in data externally applied;

writing a data value inverted from the corresponding data value of said write-in data in at least one but not all memory cells of said predetermined number of memory cells, and writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said predetermined number of memory cells, in response to said test mode signal;

accessing said predetermined number of memory cells simultaneously selected, inverting and reading stored data of said at least one memory cell in which said data inverted data value is written, and reading the stored data of said remaining memory cells of said predetermined number of memory cells in noninverted form; and

output a logic value corresponding to the data read from said predetermined number of memory cells in response to said test mode signal, wherein

said step of writing and said step of reading each include a step of inverting data only for a predetermined memory array block among said plurality of memory array blocks.

18. A dynamic type memory device comprising:

a plurality of memory cells each for storing information;

test mode signal generating means for generating a test mode designating signal designating a test mode;

selection means receiving said test mode designating signal from said test mode signal generating means and for selecting simultaneously a predetermined number of memory cells from said plurality of memory cells according to an address signal when said test mode signal designates said test mode;

writing means for receiving external data and for writing a data value inverted from the corresponding data value of said external data inputted into at least one memory cell among said predetermined number of memory cells selected by said selecting means, and also writing data values having the same corresponding values as that of said external data inputted into a remaining memory cell of said predetermined number of memory cells selected by said selecting means, in the test mode;

reading means for reading out the data of a memory cell storing the data inverted from the value of said external data inputted, and inverting the read-out data to be output, and also for reading out the data of a memory cell storing data with the same value as said external data inputted to be output, in the test mode; and

logic operation means for receiving the data outputted from said reading means to provide a logic value corresponding to the data received from said reading means, wherein

logic operation means for receiving the data outputted from said reading means to provide a logic value corresponding to the data received from said reading means, wherein

said plurality of memory cells are arranged in a memory cell array, and

said memory cell array has a plurality of subarray blocks;

each of the subarray blocks has a plurality of bit line pairs;

each of said bit line pairs has a first bit line to which the data of the memory cell selected are transmitted, and a second bit line to which the data complementary to the data on said first bit line are transmitted,

said selecting means including means for selecting one memory cell from each of said subarray blocks,

said writing means including a plurality of first internal data transmitting line pairs, one for each of said subarray blocks, said first internal data transmitting line pairs transmitting complementary internal write-in data pairs, and means for connecting said first internal data transmitting line pairs to the bit line pairs in the corresponding subarray blocks so that a manner of connection between the bit line pairs and the first internal data transmitting line pairs in at least one of the subarray blocks differs from a manner of connection therebetween in the remaining subarray blocks, and

said reading means including a plurality of second internal data transmitting line pairs, one provided for each of said subarray blocks, each of said second internal data transmitting line pairs transmitting complementary internal read-out data pair, and means for connecting said second internal data transmitting line pairs to the bit line pairs in corresponding subarray blocks so that a manner of connection between the bit line pairs and the second internal data transmitting line pairs in at least one of the subarray blocks differs from a manner of connection between the bit line pairs and the second internal data transmitting line pairs in the remaining subarray blocks.

19. A dynamic-type semiconductor memory device including a plurality of memory array blocks, each of said memory array blocks including a plurality of memory cells each of which cells stores information therein, and operable in a test mode operation for simultaneously selecting a predetermined number of memory cells from said plurality of memory array blocks, simultaneously writing information in said predetermined number of memory cells selected, and then simultaneously reading information stored in said predetermined number of memory cells, and estimating reliability of said memory device according to the information read out, said device comprising:

generating means for generating an internal test mode signal designating said test mode;

selecting means activated in response to said internal test mode signal for simultaneously selecting said predetermined number of memory cells from said memory array blocks in accordance with a received address, wherein at least one memory cells is selected in each memory array block;

receiving means for receiving write-in data values externally applied;

writing means coupled to said receiving means for writing a data value inverted from the corresponding data value of said write-in data in at least one but not all memory cells of said predetermined number of memory cells simultaneously selected, and also simultaneously writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said predetermined number of memory cells simultaneously selected;

accessing means for accessing said predetermined number of memory cells simultaneously selected, said accessing means including reading means for inverting and reading the stored data of said at least one memory cell where said inverted data is written, and simultaneously reading the stored data of said remaining memory cells as they are; and

logic means activated in response to said internal test mode signal for receiving all of the output data from said reading means and outputting a logic value corresponding to the data received, wherein

each of said plurality of memory array block comprises a plurality of bit line pairs each of which pairs includes a first bit line having data of a selected memory cell transmitted thereon and a second bit line having data complementary to the data on said first bit line is transmitted thereon,

said writing means and reading means each comprising a plurality of internal data transmitting line pairs provided respectively for each of said memory array blocks and connection means provided respectively for each of said memory array blocks for connecting a selected memory cell in a corresponding array block through a related bit line pair to a corresponding internal data transmitting line pair, connection of said connecting means corresponding to the memory array block related to said at least one memory cell being the reverse of the connection of said connecting means corresponding to the memory array block related to each of the remaining memory cells.

20. A dynamic-type semiconductor memory device including a memory cell array having a plurality of memory cells, each of said cells storing information therein, and operable in a test mode operation for simultaneously selecting a prescribed number of the memory cells in said memory cell array, simultaneously writing information in said prescribed number of memory cells selected, and then simultaneously reading information stored in said prescribed number of memory cells, and determining acceptability of said semiconductor memory device according to the information read out, said device comprising:

generating means for generating an internal test mode signal designating said test mode,

selecting means activated in response to said test mode signal for simultaneously selecting said prescribed number of memory cells from said memory array in accordance with an address externally provided,

receiving means for receiving write-in data externally applied,

writing means coupled to said receiving means for writing a data value inverted from the value of said write-in data in at least one but not all memory cells of said prescribed number of memory cells selected, and also writing data values having the same corresponding values as that of said write-in data in the remaining memory cells of said selected prescribed number of selected memory cells,

accessing means for accessing said selected prescribed number of selected memory cells, said accessing means including reading means for inverting and reading the stored data value of said at least one memory cell where said inverted data value is written, and reading the stored data values of said remaining memory cells as they are, and

logic means activated in response to said test mode signal for receiving all of the output data from said reading means and outputting a logic value corresponding to the data received, wherein

said memory cell array comprises a plurality of subarray blocks each having a plurality of bit line pairs, each of said bit line pairs having a first bit line to which a data value of a memory cell selected is transmitted, and a second bit line to which a data value complementary to the data value on said first bit line is transmitted,

said selecting means comprises means for selecting one memory cell from each of said subarray blocks,

said writing means comprises a plurality of first internal data transmitting line pairs at least one of which is provided for each of said subarray blocks, the number of said plurality of first internal data transmitting line pairs corresponding to the number of memory cells selected simultaneously, said first internal data transmitting line pairs transmitting complementary internal write-in data, and connecting means for connecting said first internal data transmitting line pairs to the bit line pairs in the corresponding subarray blocks in a first relationship in at least one but not all of the subarray blocks and in a second relationship, different from the first relationship, in the remaining subarray blocks, and

said reading means comprises a plurality of second internal data transmitting line pairs, at least one of which is provided in each of said subarray blocks, the number of said plurality of second internal data transmitting line pairs corresponding also to the number of memory cells selected simultaneously, each of said second internal data transmitting line pairs transmitting complementary internal read-out data, and means for connecting said second internal transmitting line pairs to the bit line pairs in corresponding subarray blocks so that a manner of connection between the bit line pairs and the second internal data transmitting line pairs in at least one but not all of the subarray blocks differs from a manner of connection between the bit line pairs and the second internal data transmitting line pairs in the remaining subarray blocks.