Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement

• US 5,208,782 A
• Filed: 05/29/1992
• Issued: 05/04/1993
• Est. Priority Date: 02/09/1989
• Status: Expired due to Term

• Current Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Original Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Inventors: Nakamura, Hisashi, Iwai, Hidetoshi, Uchiyama, Hiroyuki, Miyazawa, Kazuyuki, Ishihara, Masamichi, Takahashi, Yasushi, Oshima, Kazuyoshi, Maeda, Toshio, Sasaki, Toshio, Sakai, Osamu, Hori, Ryoichi, Miyamoto, Eiji, Kasama, Yasuhiro, Matsuura, Hiromi, Sakuta, Toshiyuki, Tazunoki, Masanori
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): LANE, JOHN A
• Application Number:
  US07/892,708
• Time in Patent Office: 340 Days
• Field of Search: 365/51, 365/63, 365/230.03, 357/45, 357/70
• US Class Current: 365/230.03
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Claims

1. A semiconductor integrated circuit device comprising:

a first memory block formed in a main surface of a semiconductor chip, which includes a first memory array having memory cells arranged in a matrix form, a first address decoder coupled to said first memory array and a first data input/output circuit coupled to said first memory array;

a second memory block formed in said main surface of said semiconductor chip, which includes a second memory array having memory cells arranged in a matrix form, a second address decoder coupled to said second memory array and a second data input/output circuit coupled to said second memory array;

a first external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said first memory block, said first external terminal being formed to be closer to the first memory block than to the closet peripheral edge of the semiconductor chip to shorten the connection distance between the first external terminal and the first memory block;

a second external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said second memory block, said second external terminal being formed to be closer to the second memory block than to the closest peripheral edge of the semiconductor to shorten the connection distance between the second external terminal and the second memory block;

a lead attached on said main surface of said semiconductor chip via an insulator;

a first bonding wire for coupling said lead and said first external terminal; and

a second bonding wire for coupling said lead and said second external terminal,

wherein said lead crosses a peripheral edge of the chip to extend from outside of said chip to the interior of said chip, wherein said lead has a first end located over the interior of said chip, and wherein at least one of said first and second bonding wires extends from a portion of said lead located over the interior of said chip, other than the first end of said lead, to shorten the distance for the connection between the lead and the corresponding first or second external terminal.

2. A semiconductor integrated circuit device according to claim 1, further comprising:

a first circuit for outputting a signal for selecting either one of said first and second memory blocks.

3. A semiconductor integrated circuit device according to claim 2, further comprising:

a first circuit for outputting a first address signal supplied to said first and second memory blocks and a second address signal supplied to said first circuit.

4. A semiconductor integrated circuit device according to claim 3, wherein said memory cells are dynamic type memory cells.

5. A semiconductor integrated circuit device according to claim 4, further comprising:

a third circuit for outputting a third address signal supplied to said first and second memory blocks when said semiconductor integrated circuit device is in a refresh mode.

6. A semiconductor integrated circuit device according to claim 5, wherein said first memory block has a first address selector for supplying either one of said first and third address signals to said first address decoder.

7. A semiconductor integrated circuit device according to claim 6, wherein said second memory block has a second address selector for supplying either one of said first and third address signals to said second address decoder.

8. A semiconductor integrated circuit device according to claim 7, further comprising:

a fourth circuit for outputting a timing signal to said first memory block which is selected by said first circuit.

9. A semiconductor integrated circuit device according to claim 7, wherein said first and second external terminals are address signal terminals.

10. A semiconductor integrated circuit device according to claim 7, wherein said first and second external terminals are row address strobe signal terminals.

11. A semiconductor integrated circuit device according to claim 7, wherein said first and second external terminals are column address strobe signal terminals.

12. A semiconductor integrated circuit device according to claim 7, wherein said first and second external terminals are write enable signal terminals.

13. A semiconductor integrated circuit device according to claim 9, wherein said first and second bonding wires are coated with insulators.

14. A semiconductor integrated circuit device according to claim 7, wherein selecting signals for selecting predetermined ones of said memory cells are formed on the basis of said first address signal when said semiconductor integrated circuit device is in a normal mode, wherein said selecting signal for selecting said first and second memory blocks is formed on the basis of said second address signal, and wherein selecting signals for selecting predetermined ones of said memory cells are formed on the basis of said third address signal when said semiconductor integrated circuit device is in a refresh mode.

15. A semiconductor integrated circuit device comprising:

a first memory block formed in a main surface of a semiconductor chip, which includes a first memory array having memory cells arranged in a matrix form, a first address decoder coupled to said first memory array and a first data output circuit coupled to said first memory array;

a second memory block formed in said main surface of said semiconductor ship, which includes a second memory array having memory cells arranged in a matrix form, a second address decoder coupled to said second memory array and a second data output circuit coupled to said second memory array;

a first external terminal formed in said main surface of said semiconductor chip, to provide an external connection point for internal elements of said first memory, said first external terminal being formed to be closer to the first memory block than to the closest peripheral edge of the semiconductor chip to shorten the connection distance between the first external terminal and the first memory block;

a first lead attached on said main surface of said semiconductor chip via an insulator;

a first coupling means for coupling said first lead and said first external terminal; and

a second coupling means for coupling said first lead and said second external terminal,

wherein said lead crosses a peripheral edge of the chip to extend from outside of said chip to the interior of said chip, wherein said lead has a first end located over the interior of said chip, and wherein at least one of the first and second coupling means extends from a portion of said lead located over the interior of said chip, other than the first end of said lead, to shorten the distance for connection between the lead and the corresponding first or second coupling means.

16. A semiconductor integrated circuit device according to claim 15, further comprising:

a third external terminal formed in said main surface of said semiconductor chip, which corresponds to said first memory block;

a fourth external terminal formed in said main surface of said semiconductor chip, which corresponds to said second memory block;

a second lead attached on said main surface of said semiconductor chip via an insulator;

a third coupling means for coupling said second lead and said third external terminal; and

a fourth coupling means for coupling said second lead and said fourth external terminal.

17. A semiconductor integrated circuit device according to claim 16, further comprising:

a first circuit for outputting a signal for selecting either one of said first and second memory blocks.

18. A semiconductor integrated circuit device according to claim 17, further comprising:

a second circuit for outputting a first address signal supplied to said first and second memory blocks and a second address signal supplied to said first circuit, wherein selecting signals for selecting predetermined ones of said memory cells are formed on the basis of said first address signal, and further wherein said selecting signal for selecting said first and second memory blocks is formed on the basis of said second address signal.

19. A semiconductor integrated circuit device according to claim 18, wherein said memory cells are dynamic type memory cells.

20. A semiconductor integrated circuit device according to claim 19, wherein said first and second external terminals are address signal terminals.

21. A semiconductor integrated circuit device according to claim 20, wherein said third and fourth external terminals are address strobe signal terminals.

22. A semiconductor integrated circuit device according to claim 19, wherein said first, second, third and fourth coupling means are bonding wires.

23. A semiconductor integrated circuit device according to claim 22, wherein said bonding wires are coated with insulators.

24. A semiconductor integrated circuit device comprising:

a plurality of memory blocks formed in a main surface of a semiconductor chip, each of which includes a memory array having memory cells arranged in a matrix form, an address decoder coupled to said memory array and a data output circuit coupled to said memory array;

a plurality of external terminal groups formed in said main surface of said semiconductor chip, each of which external terminals corresponds to a respective one of said memory blocks to provide an external connection point for internal elements of its corresponding memory block, and each of which is closer to its corresponding memory block than to the closest peripheral edge to shorten the connection distances between the external terminals and their corresponding memory blocks;

first and second leads attached on said main surface of said semiconductor chip via an insulator;

a first coupling means for coupling said first lead and said external terminals which belong to different external terminal groups to each other; and

a second coupling means for coupling said second lead and said external terminals which belong to different external terminal groups to each other,

wherein said first and second leads each cross a peripheral edge of the chip to extend from outside of the chip to the interior of the chip, wherein each of the first and second leads has a first end located over the interior of said chip, wherein said first coupling means extends from a portion of the first lead, other than the first end thereof, to shorten the distance for connection between the first lead and one of the plurality of external terminals, and wherein the second coupling means extends from a portion of a second lead, other than the first end thereof, to shorten the distance for connection between the second lead and another one of the plurality of external terminals.

25. A semiconductor integrated circuit device according to claim 24, wherein said plurality of memory blocks are arranged in a matrix form.

26. A semiconductor integrated circuit device according to claim 25, wherein each of said external terminal groups is commonly used for said memory blocks which are arranged closely to each other.

27. A semiconductor integrated circuit device according to claim 26, wherein said first and second coupling means are bonding wires.

28. A semiconductor integrated circuit device according to claim 27, wherein said bonding wires are coated with insulators.