Subscriber loop tester for telephone switching systems

• US 5,208,846 A
• Filed: 09/03/1991
• Issued: 05/04/1993
• Est. Priority Date: 09/03/1991
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Edwards, James W., Lubarsky, Andre Jr., Hammond, John A.
• Primary Examiner(s): Schreyer, Stafford
• Application Number:
  US07/758,971
• Time in Patent Office: 609 Days
• Field of Search: 379/27, 379/29, 379/28, 379/15, 379/16, 375/10
• US Class Current: 379/9.06
• CPC Class Codes: H04M 3/245 for ISDN systems
• CPC Class Codes: H04Q 11/045 Selection or connection testing arrangements

Abstract

A subscriber loop tester for testing local loops of telephone switching networks has a partitioned "U" interface and an internal bus architecture for converting various transceiver circuit output data formats to a common data format. The "U" interface has a high impedance transformer meeting bandwidth and line matching requirements for different line codes and protocols for ISDN telecommunication systems. The transformer is selectively coupled to option cards each containing circuitry having AC and DC terminations matching specific line codes and protocols for ISDN telecommunications systems and other types of telecommunications systems. The option cards further contain programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss. A high speed bus is selectively coupled to the option cards for coupling the formatted transceiver circuit output data between the cards and a digital bus translator. The digital bus translator selectively configures the high speed bus for the transceiver output data format of the selected option card and converts the formatted output data received on the high speed bus to a common data format. Multiple source and destination audio paths in the subscriber loop tester are controlled by an audio switching matrix.

Claims

1. A subscriber loop tester for transmitting outgoing telecommunications signals to and receiving incoming telecommunications signals from telephone switching systems implementing different data line codes and protocols and telecommunications standards comprising:

a partitioned "U" interface having a high impedance transformer coupled to receive the telecommunications signals and meeting the bandwidth and line matching requirements for different line codes and protocols implemented in an ISDN telecommunications system;

a plurality of circuits selectively coupled to receive the telecommunications signals from the high impedance transformer with each circuit having AC and DC terminations matching a specific line code and protocol and programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss, the terminations and attenuators being coupled to a transceiver circuit for generating an output having a specific data format;

a digital bus translator for converting the specific data formats of the various transceiver circuits on the plurality of circuits to a common data format;

a high speed bus for coupling the output of the transceiver circuits on the plurality of circuits to the digital bus controller, the high speed bus being selectively coupled to each of the plurality of circuits and selectively configured by the digital bus translator for the specific data format of the transceiver circuit; and

means for controlling source and destination audio paths for voice telecommunications signals within the subscriber loop tester

2. The subscriber loop tester as recited in claim 1 wherein the plurality of circuits further comprise non-ISDN data communications standard circuits.

3. The subscriber loop tester as recited in claim 2 further comprising a means for switching the telecommunications signals to the non-ISDN data communications standard circuits, the switching means interposed between the telephone switching network and the partitioned "U" interface.

4. The subscriber loop tester as recited in claim 2 wherein each of the plurality of circuits reside on a removable circuit board, the circuit boards being connected to a common controller bus.

5. The subscriber loop tester as recited in claim 1 wherein the digital bus translator is a field programmable gate array.

6. The subscriber loop tester as recited in claim 1 wherein the audio path controlling means is an audio switching matrix for coupling incoming and outgoing voice telecommunications signals to and from the plurality of circuits and to and from analog voice transducers.

7. The subscriber loop tester as recited in claim 1 wherein the high speed bus is a four wire bus for coupling transmit, receive, clock, and framing data.

8. A partitioned "U" interface for a subscriber loop tester comprising:

a high impedance transformer meeting the bandwidth and line matching requirements for different line codes and protocols implemented in an ISDN telecommunications system; and

a plurality of circuits selectively coupled to receive the telecommunications signals from the high impedance transformer with each circuit having AC and DC terminations matching a specific line code and protocol and programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss.

9. The partitioned "U" interface as recited in claim 8 wherein each of the plurality of circuits reside on a removable circuit board, the circuit boards being connected to a common controller bus.

10. An internal bus architecture for a subscriber loop tester comprising:

a plurality of circuits selectively coupled to receive telecommunications signals from an external source with each circuit having AC and DC terminations matching a specific line code and protocol and programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss, the terminations and attenuators being coupled to a transceiver circuit for generating an output having a specific data format;

a digital bus translator for converting the specific data formats of the various transceiver circuits on the plurality of circuits to a common data format;

a high speed bus for coupling the output of the transceiver circuits on the plurality of circuits to the digital bus controller, the high speed bus being selectively coupled to each of the plurality of circuits and selectively configured by the digital bus translator for the specific data format of the transceiver circuit.

11. The internal bus architecture for a subscriber loop tester as recited in claim 10 wherein the digital bus translator is a field programmable gate array.

12. The internal bus architecture for a subscriber loop tester as recited in claim 10 wherein the high speed bus is a four wire bus for coupling transmit, receive, clock, and frame data.

13. A subscriber loop tester for transmitting outgoing telecommunications signals to and receiving incoming telecommunications signals from telephone switching systems implementing different data line codes and protocols and telecommunications standards comprising:

a plurality of circuits selectively coupled to receive the telecommunications signals with each circuit having AC and DC terminations matching a specific line code and protocol of a telecommunications standard and programmable attenuators for producing a proper nominal signal level as a function of the specific line code and protocol and providing variable insertion loss, the terminations and attenuators being coupled to a transceiver circuit for generating an output having a specific data format;

a digital bus translator for converting the specific data formats of the various transceiver circuits on the plurality of circuits to a common data format;

a high speed bus for coupling the output of the transceiver circuits on the plurality of circuits to the digital bus controller, the high speed bus being selectively coupled to each of the plurality of circuits and selectively configured by the digital bus translator for the specific data format of the transceiver circuit; and

means for controlling source and destination audio paths for voice telecommunications signals within the subscriber loop tester.

14. The subscriber loop tester as recited in claim 13 wherein selected circuits of the plurality of circuits have a high impedance transformer meeting the bandwidth and line matching requirements for different line codes and protocols implementing ISDN telecommunications standards.

15. The subscriber loop tester as recited in claim 13 wherein each of the plurality of circuits reside on a removable circuit board, the circuit boards being connected to a common controller bus.

16. The subscriber loop tester as recited in claim 13 wherein the digital bus translator is a field programmable gate array.

17. The subscriber loop tester as recited in claim 13 wherein the audio path controlling means is an audio switching matrix for coupling incoming and outgoing voice telecommunications signals to and from the plurality of circuits and to and from analog voice transducers.

18. The subscriber loop tester as recited in claim 13 wherein the high speed bus is a four wire bus for coupling transmit, receive, clock, and frame data.