Selective plating method for forming integral via and wiring layers

• US 5,209,817 A
• Filed: 08/22/1991
• Issued: 05/11/1993
• Est. Priority Date: 08/22/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kumar, Ananda, Berger, Daniel G., Wong, Kwong H., Prasad, Keshav B., LaMaire, Susan J., Ray, Sudipta K., Ahmad, Umar M.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/748,445
• Time in Patent Office: 628 Days
• Field of Search: 156/643, 156/644, 156/655, 156/656, 156/659.1, 156/668, 29/852, 29/874, 29/876, 29/884, 361/417, 361/420, 361/425, 427/97, 204/15
• US Class Current: 216/18
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/0187 with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2203/0597 Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
• CPC Class Codes: H05K 2203/072 Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/061 Etching masks
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/184 using masks
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4605 made from inorganic insulating material
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/465 by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4661 Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387

Abstract

In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

Claims

1. A method of fabricating wiring and via conductors comprising:

forming a via opening in a dielectric layer extending from an upper surface of the dielectric layer through said dielectric layer with said dielectric layer forming a wall of said via;

forming a thin conductive seed layer over the upper surface of said dielectric layer and the wall defining said via opening;

forming a masking layer on said seed layer;

forming openings in said masking layer that expose said seed layer in the wall of the via opening and in a desired wiring pattern;

electroplating conductive material onto the exposed portions of said seed layer so that isotropic deposition of said conductive material fills said via opening in said dielectric layer with the upper surface of the conductive material that fills said via opening co-planar with the upper surface of the conductive material in said wiring pattern.

3. A method of fabricating wiring and via conductors as in claim 1 including the additional step of planarizing said dielectric layer.

5. A method of fabricating wiring and via conductors as in claim 1 wherein said via opening has a diameter equal to approximately one-half the plating thickness.

7. A method of fabricating wiring and via conductors as in claim 3 wherein said via opening has a diameter equal to approximately one-half the plating thickness.

2. A method of fabricating wiring and via conductors comprising:

a. forming a via opening in a first dielectric layer extending from an upper surface of the dielectric layer through said dielectric layer with said dielectric layer forming a wall of said via;

b. forming a thin conductive seed layer over the upper surface of said dielectric layer and the wall defining said via opening;

c. forming a masking layer on said seed layer;

d. forming openings in said masking layer that expose said seed layer in the wall of the via opening and in a desired wiring pattern;

e. electroplating conductive material onto the exposed portions of said seed layer so that isotropic deposition of said conductive material fills said via opening in said dielectric layer with the upper surface of the conductive material that fills said via opening co-planar with the upper surface of the conductive material in said wiring pattern;

f. removing said dielectric masking layer; and

g. coating the assembly of set forth in paragraph e with a second dielectric layer and repeating the steps a through e to form a second wiring and via conductive layer.

4. A method of fabricating wiring and via conductors as in claim 2 including the further steps of planarizing said first dielectric layer and planarizing said second dielectric layer.

6. A method of fabricating wiring and via conductors as in claim 2 wherein said via opening has a diameter equal to approximately one-half the plating thickness.

8. A method of fabricating wiring and via conductors as in claim 4 wherein said via opening has a diameter equal to approximately one-half the plating thickness.

10. A method of fabricating wiring and via conductors as in claim 6 wherein said via opening has a diameter equal to approximately one-half the plating thickness.

9. A method of fabricating wiring and via conductors comprising:

forming a via opening in a dielectric layer extending from an upper surface of the dielectric layer through said dielectric layer with said dielectric layer forming a wall of said via opening;

forming a wiring pattern opening in said dielectric layer extending from said upper surface of the dielectric layer through the dielectric layer with the dielectric layer forming a wall of said wiring pattern opening;

forming a thin conductive seed layer over the upper surface of said dielectric layer, over the via opening including the wall defining said via opening, and over the wiring pattern opening including the wall defining the wire pattern opening;

removing said conductive seed layer from said upper surface of said dielectric layer, from the wall defining said via opening, and from the wall defining said wire pattern opening;

electrolessly plating conductive material onto the remaining portions of said seed layer so that isotropic deposition of said conductive material fills said via opening and said wire pattern openings in said dielectric layer with the upper surface of the conductive material that fills said via opening co-planar with the upper surface of the conductive material that fills said wiring pattern openings.