Process for manufacturing semiconductor integrated circuit device

• US 5,210,041 A
• Filed: 07/18/1991
• Issued: 05/11/1993
• Est. Priority Date: 07/24/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakata, Kensuke, Kobayashi, Tsuneo
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/732,280
• Time in Patent Office: 663 Days
• Field of Search: 437/8, 437/209, 437/194, 437/195, 437/190
• US Class Current: 438/7
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

A wafer manufacturing process for a semiconductor integrated circuit device, including testing the semiconductor wafer at a unit of chip each time a predetermined treating step is performed. The test results are feed to a computer control for restricting succeeding treatments or further testing of chip or chips based on the test results and the predetermined number of chips to be produced. Semiconductor wafer(s) is/are loaded for manufacture on the basis of the number of chips to be produced, taking into account of any losses created by defective chips detected during each testing step and any excess created by additional semiconductor wafers loaded in response to shortages created by defects. The excess chips are monitored by the computer control and any succeeding treatments or further testing of the excess chips are halted to save time and manufacturing costs.

Claims

1. In a wafer process for manufacturing a semiconductor integrated circuit device by subjecting a semiconductor wafer to a plurality of treating steps,

a process for manufacturing a semiconductor integrated circuit device, comprising the repeated steps of:

testing said semiconductor wafer at a unit of chip each time a predetermined one of said treating steps is ended;

preparing control data for loading another semiconductor wafer on the basis of the data of each of said chips and feeding the control data back to a predetermined treating step of the wafer process if it is decided in accordance with the data of each chip based upon the test results that the number of non-defective chips at the testing stage is short of the necessary number for the testing step;

performing said tests of the semiconductor wafers including said another one; and

monitoring the data of the chips of the initially loaded semiconductor wafer and the added semiconductor wafer synthetically and feeding control data for loading another semiconductor wafer, each time it is decided that the number of non-defective chips is short of the necessary number for the testing step in its entirety, back to a predetermined treating step of the wafer process.

2. A process for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of:

feeding control data to restrict any further treating step, any further testing step of a chip or chips which have been detected as being defective during any of the testing steps.

3. A process for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the control data for restricting are fed forward to the step after the end of said wafer process.

4. A process for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of:

feeding control data to restrict any further treating step and any testing step of a chip or chips which exceed a predetermined number of non-defective chips desired, in response to the test results which indicate the total number of non-defective chips available.

5. A process for manufacturing a semiconductor integrated circuit device according to claim 1, wherein if a defect is discovered by comparing the result of the test and the designed reference data of the treating step preceding the test, control data for revising the defect are prepared on the basis of the compared data to revise the defect immediately after the test on the basis of the control data.

6. A process for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the pattern of a mask used in the treating step before said test is revised immediately after the test on the basis of the control data for revising the defect.

7. A process for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the treating conditions of the treating step before said test are revised immediately after the test on the basis of the control data for revising the defect.

8. A process for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said process for manufacturing a semiconductor integrated circuit device is controlled by using a computer.

9. In a wafer process for manufacturing a semiconductor integrated circuit device by subjecting a semiconductor wafer to a plurality of treating steps,

a process for manufacturing a semiconductor integrated circuit device, comprising the commands of:

testing said semiconductor wafer at a unit of chip each time a predetermined one of said treating steps is ended;

preparing control data for loading another semiconductor wafer on the basis of the data of each of said chips and feeding the control data back to a predetermined treating step of the wafer process if it is decided in accordance with the data of each chip at the testing stage that the number of non-defective chips is short of the necessary number for the testing step;

repeating performing said tests of the semiconductor wafers including said another one, monitoring the data of the chips of the initially loaded semiconductor wafer and the added semiconductor wafer synthetically, and feeding control data for loading another semiconductor wafer, each time it is decided that the number of non-defective chips is short of the necessary number for the testing step in its entirety, back to a predetermined treating step of the wafer process;

preparing control data for restricting the chip to be subjected to a treating step before the test and a testing step, if it is decided as a result of the data of said chips that the number of non-defective chips exceeds the necessary number at the testing stage, and feeding said control data as the treating data for another succeeding semiconductor wafer back to the treating step and testing step preceding the test by at least one; and

preparing control data for restricting a chip to be subjected to the treating step after the test on the basis of the data of said chip, and feeding said control data back to a treating step preceding the test by at least one.

10. A process for manufacturing a semiconductor integrated circuit device, according to claim 9, wherein, if a defect is discovered by comparing the result of the test and the designed reference data of the treating step preceding the test, control data for revising the defect are prepared on the basis of the compared data to revise the defect immediately after the test on the basis of the control data.

11. A process for manufacturing a semiconductor integrated circuit device, according to claim 9, wherein the data for restricting the chip to be subjected to the treating step after the test are fed forward to the step after the end of said wafer process.

12. A process for manufacturing a semiconductor integrated circuit device according to claim 9, wherein said process for manufacturing a semiconductor integrated circuit device is controlled by using a computer.