Memory circuit with extended valid data output time

• US 5,210,715 A
• Filed: 08/27/1990
• Issued: 05/11/1993
• Est. Priority Date: 06/27/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/573,598
• Time in Patent Office: 988 Days
• Field of Search: 307/443, 307/481, 307/594, 307/265, 307/597, 307/601, 307/603, 307/279, 307/479, 365/189.05, 365/194, 365/203, 365/233.5
• US Class Current: 365/194
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Claims

1. An output buffer including an asymmetrical delay circuit, said buffer being operable such that said buffer responds slower to input transitions from a first state to a second state than said buffer responds to input transitions from said second state to said first state.