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Memory circuit with extended valid data output time

  • US 5,210,715 A
  • Filed: 08/27/1990
  • Issued: 05/11/1993
  • Est. Priority Date: 06/27/1988
  • Status: Expired due to Term
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1. An output buffer including an asymmetrical delay circuit, said buffer being operable such that said buffer responds slower to input transitions from a first state to a second state than said buffer responds to input transitions from said second state to said first state.

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