Configuration of SRAMS as logical FIFOS for transmit and receive of packet data

• US 5,210,749 A
• Filed: 05/29/1990
• Issued: 05/11/1993
• Est. Priority Date: 05/29/1990
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Firoozmand, Farzin
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HSU, ALPUS
• Application Number:
  US07/529,363
• Time in Patent Office: 1,078 Days
• Field of Search: 370/60, 370/60.1, 370/85.1, 370/85.4, 370/85.5, 370/85.6, 370/85.12, 370/85.15, 370/94.1, 370/110.1, 340/825.05, 340/825.5, 340/825.51, 340/825.52, 359/115, 359/118, 359/135
• US Class Current: 370/463
• CPC Class Codes: H04L 47/521 Static queue service slot or fixed bandwidth allocation
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9036 Common buffer combined with individual queues

Abstract

Data arranged in packets are transferred between a system memory and a network bus through a SRAM configured by software pointers as first in-first out memories for transmitting (transmit FIFO) and for receiving (receive FIFO). The packets of data stored in the transmit and receive FIFOs are demarked from each other and classified by tag and status bits at the end of the last word of each packet. Data to be transmitted on the network bus is transferred from the system memory to the transmit FIFO, and data received from the network is stored in the receive FIFO. To maximize data throughput, when either at least a predetermined amount of data or a complete packet is stored in the transmit FIFO, the data is transmitted to the network while data is being received from the system memory. When at least a predetermined amount of data is stored in the receive FIFO, data is transferred to the system memory while network data is incoming from the network. One application of the invention is in a Fiber Distributed Data Interface (FDDI).

Claims

1. For a network adapter controlling flow of data arranged in packets from a system memory to a network, comprising:

buffer memory means for storing data in the form of the packets each having one end marked by a tag bit;

means for configuring said buffer memory means as a logical first in-first out memory (FIFO);

means for detecting a request for transmission of data to the network;

first means responsive to said request for transmission to said network for transferring data from said system memory, one packet at a time, to said FIFO;

means responsive to said tag bit detecting the end of a packet; and

second means responsive to said tag bit detecting means for transferring said data from said FIFO to said network while data is incoming from the system memory to said FIFO.

2. The adapter of claim 1, including packet detecting means for detecting the presence in said FIFO of at least one packet of said data to be transmitted to the network, and wherein said second means includes means responsive to said packet detecting means for transferring said data in said FIFO to said network.

3. The adapter of claim 1, including transmit data threshold detecting means for detecting the presence in said FIFO of at least a predetermined amount of data to be transmitted to said network, and wherein said second means includes means responsive to said transmit data threshold detecting means for transferring said data in said FIFO to said network.

4. The adapter of claim 3, including packet detecting means for detecting the presence in said FIFO of at least one packet of said data, and wherein said second means includes means responsive to said packet detecting means and said transmit data threshold detecting means for transferring said data to said network when either at least a packet of data or at least the predetermined amount of data is in said FIFO.

5. The adapter of claim 1, including receive data threshold detecting means for detecting the presence in said FIFO of at least a predetermined amount of data received from the network, and wherein said second means includes means responsive to said receive data threshold detecting means for transferring said data in said FIFO to said system memory means.

6. The adapter of claim 3, wherein said FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said FIFO and a SHADOW WRITE pointer pointing to the end of a full frame stored in said FIFO, wherein said transmit data threshold detecting means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

7. The adapter of claim 6, including a register storing a data threshold value wherein said transmit data threshold detecting means includes means for comparing the difference between said READ pointer and said WRITE pointer with said data threshold value.

8. The adapter of claim 3, including a register storing a data threshold value, and wherein said transmit data threshold detecting means includes means for comparing the content of said FIFO and said data threshold value.

9. For a network adapter controlling flow of data arranged in packets between a system memory and a network, comprising:

first memory means for storing transmit data;

means for configuring said first memory means as a first logical first in-first out memory (transmit FIFO);

means for detecting a request for transmission of data to the network;

first means responsive to said request for transmission to said network for transferring data from said system memory, one packet at a time, to said transmit FIFO;

second means for transferring said data from said transmit FIFO to said network while said transmit FIFO is receiving data from said system memory;

second memory means for storing receive data;

means for configuring said second memory means as a second logical first in-first out memory (receive FIFO);

means for detecting data incoming from the network to be stored in the system memory;

third means for transferring data from said network to said receive FIFO; and

fourth means detecting a predetermined amount of data in said receive FIFO for transferring said predetermined amount of data from said receive FIFO to said system memory while said receive FIFO is receiving data from said network.

10. The adapter of claim 9, wherein data stored in said FIFO is in the form of packets each having one end demarked by a tag bit and wherein said adapter further includes means response to said tag bit detecting the end of a packet.

11. For a network adapter controlling flow of data arranged in packets between a system memory and a network, apparatus comprising:

first buffer memory means for storing data to be transmitted on said network;

means for configuring said first buffer memory means as a first logical first in-first out memory (transmit FIFO);

first detecting means for detecting a request for transmission of data to the network;

means responsive to said first detecting means for transferring data from said system memory, one packet at a time, to said transmit FIFO;

second detecting means for detecting the presence in said transmit FIFO of at least one full packet of said transmit data;

third detecting means for detecting the presence in said transmit FIFO of at least a predetermined amount of transmit data;

means responsive to said second and third detecting means for transferring data from said transmit FIFO to said network when either at least a full packet of data or at least said predetermined amount of data is stored in said transmit FIFO;

second memory means for storing data received from said network;

means for configuring said second memory means as a second logical first in-first out memory (receive FIFO);

fourth detecting means for detecting data incoming from the network to be stored in the system memory;

means for transferring data from said network to said receive FIFO;

fifth detecting means for detecting a predetermined amount of data stored in said receive FIFO from said network; and

means responsive to said fifth detecting means for transferring said predetermined amount of data from said receive FIFO to said system memory.

12. The apparatus of claim 11, wherein said transmit FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said transmit FIFO, and a SHADOW WRITE pointer pointing to the end of a full frame stored in said transmit FIFO, wherein said second detecting means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

13. The apparatus of claim 12, including a register storing a data threshold value, and wherein said third detecting means includes means for comparing the difference between said READ pointer and said WRITE pointer with said data threshold value.

14. The apparatus of claim 11, including a register storing a data threshold value, and wherein said third detecting means includes means for comparing the content of said transmit FIFO and said data threshold value.

15. For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet bit, a network controller, comprising:

a random access memory;

means for defining in said random access memory a buffer memory configured as a transmit FIFO;

means for transferring from said system memory means to said transmit FIFO successive frames of data demarked by said end of packet (tag) bits and forming a queue to be transmitted;

first detector means for detecting said tag bits to determine that at least one full frame of data is stored in said transmit FIFO;

second detector means for detecting that at least a predetermined amount of data is stored in said transmit FIFO; and

means responsive to at least one of said first and second detector means for transmitting the content of said transmit FIFO to a network.

16. The controller of claim 15, wherein said transferring means includes first means for transferring frames of data to said transmit FIFO while said transmit FIFO is transmitting to said network.

17. The controller of claim 15, wherein said transmit FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said transmit FIFO, and a SHADOW WRITE pointer pointing to the end of a full frame stored in said transmit FIFO, wherein said first detector means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

18. The controller of claim 17, wherein said second detector means includes means for comparing the difference between said READ pointer and said WRITE pointer with said data threshold value.

19. The controller of claim 15, including a register storing a data threshold value, and wherein said second detector means includes means for comparing the content of said transmit FIFO and said data threshold value.

20. For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet bit, a network controller, comprising:

a random access memory;

means for defining in said random access memory a buffer memory configured as a receive FIFO;

means for storing in said receive FIFO incoming receive data packets demarked by said end of packet (tag) bits and forming a receive queue;

means for storing a receive data threshold value;

means for detecting that the content of said receive FIFO exceeds said receive data threshold value; and

means responsive to said detecting means for transferring data from said receive FIFO to said system memory means.

21. The controller of claim 20, wherein said receive FIFO is defined by START and END pointers, and including READ and WRITE pointers, a SHADOW WRITE pointer pointing to the beginning of the latest frame being received in the receive FIFO, and a receive threshold value, wherein said receive data is transferred to said system memory means when said write pointer exceed said threshold value and when said receive data is to be flushed, the write pointer is replaced by the shadow write pointer.

22. A method of controlling flow of data arranged in packets each having one end marked by a tag bit between a system memory and a network bus, comprising the steps of:

configuring a first memory as a first logical first in-first out memory (transmit FIFO);

detecting a request for transmission of data to the network bus;

in response to a request for transmission to said network bus, transferring data from said system memory, one packet at a time, to said transmit FIFO;

detecting the tag bit defining the end of a packet; and

in response to occurrence of the tag bit transferring said data from said transmit FIFO to said network bus while data is incoming from said system memory to said transmit FIFO.

23. The method of claim 22, including the additional steps of detecting the presence in said transmit FIFO of at least one full packet of said data, and in response, transferring said data to said network bus.

24. The method of claim 22, including the additional steps of detecting the presence in said transmit FIFO of at least a predetermined amount of data, and in response, transferring said data to said network bus.

25. The method of claim 24, including the additional steps of detecting the presence in said transmit FIFO of at least a predetermined amount of data, and in response, transferring said data to said network bus when either at least a packet of said data or at least the predetermined amount of data is stored in the transmit FIFO.

26. The method of claim 22, including the additional steps of

configuring a second memory as a second logical first in-first out memory (receive FIFO);

detecting data incoming from said network bus to be stored in said system memory;

transferring data from said network bus to said receive FIFO;

detecting a predetermined amount of data stored in said receive FIFO from said network bus; and

in response,

transferring said data from said receive FIFO to said system memory.

27. For an adapter for a network including a plurality of processors and system memory means for storing frames of data arranged in a plurality of different queues, the frames of each queue having a priority different from the priorities of frames of data of the other queues, apparatus for controlling transmission of said frames of data between said system memory means and said network, comprising:

a buffer memory configured to have a plurality of separate logical first in-first out (FIFO) memory regions for storing respectively the plurality of queues of framed data to be transmitted to or received from the network, each of said FIFO memory regions storing one of said queues;

first data controller means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding FIFO memory regions of said buffer memory; and

means for transmitting said framed data, stored in said FIFO memory regions of said output buffer memory, to said network while data is incoming from said system memory means to said FIFO memory regions of said buffer memory.

28. The apparatus of claim 27, including

second data controller means for controlling flow of framed data from said network to corresponding FIFO memory regions of said buffer memory, and

means for transmitting said framed data, stored in said FIFO memory regions of said output buffer memory, to said system memory means while data is incoming from said network to said buffer memory.

29. The apparatus of claim 27, including transmit frame detecting means for detecting the presence in said buffer memory of at least one full frame of transmit data, and means responsive to said transmit frame detecting means for transferring transmit data to said network.

30. The apparatus of claim 29, including transmit data threshold detecting means for detecting the presence in said buffer memory of at least a predetermined amount of transmit data, including means responsive to said transmit data threshold detecting means for transferring said data to said network.

31. The apparatus of claim 29, further including transmit data threshold detecting means for detecting the presence in said buffer memory of at least a predetermined amount of transmit data, and wherein said second data controller means includes means responsive to said frame detecting means and said transmit data threshold detecting means for transferring said data to said network when either at least a full frame of data or at least the predetermined amount of data is in said buffer memory.

32. For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors, each including a system memory means for storing frames of data arranged in a plurality of queues, each queue having a transmit priority different from the transmit priorities of the other queues, and an optical medium forming a digital data communication path among said processors, a network controller, comprising:

first means implementing a timed token data protocol for accessing said optical medium;

a random access memory forming an output buffer;

second means for configuring in said random access memory a plurality of separate logical FIFOs for respectively storing therein said plurality of queues having different transmit priorities, each of said logical FIFOs storing one of said queues;

means for controlling flow of said framed data to corresponding logical FIFOs in said buffer memory, said framed data flow controlling means including first means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding logical FIFOs in said buffer memory, and second means for transmitting said framed data, stored in said logical FIFOs to said medium while data is incoming from said system memory means to said FIFOs in said buffer memory.

33. The network controller of claim 32, including transmit frame detecting means for detecting the presence in said buffer memory of at least one full frame of transmit data, and means responsive to said transmit frame detecting means for transferring transmit data to said optical medium.

34. The controller of claim 33, further including transmit data threshold detecting means for detecting the presence in said buffer memory of at least a predetermined among of transmit data, and wherein said transfer means includes means responsive to said frame detecting means and said transmit data threshold detecting means for transferring said data to said optical medium when either at least a full frame of data or at least the predetermined amount of data is in said buffer memory.

35. The controller of claim 32, including transmit data threshold detecting means for detecting the presence in said buffer memory of at least a predetermined amount of transmit data, including means responsive to said transmit data threshold detecting means for transferring said data to said optical medium.

36. The controller of claim 32, wherein each said logical FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said logical FIFO and a SHADOW WRITE pointer pointing to the end of a full frame stored in said logical FIFO, and wherein said data flow controlling means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

37. The controller of claim 36, including a register storing a data threshold value, and wherein said data flow controlling means includes means for comparing the content of said logical FIFO and said data threshold value.

38. The controller of claim 35, wherein said transmit data threshold detecting means includes means for comparing the difference between said READ pointer and said WRITE pointer with said data threshold value.

39. The controller of claim 32, including receive data threshold detecting means for detecting the presence in said logical FIFO of at least a predetermined amount of receive data from the optical medium and wherein said data flow controller means includes means responsive to said receive data threshold detecting means for transferring said receive data in said logical FIFO to said system memory means.

40. The controller of claim 32, including a physical FIFO memory establishing a single signal flow path for said framed data between said system memory means and said buffer memory.

41. For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors each having system memory means for storing frames of data arranged in a plurality of different queues, the frames of each queue having a priority different from the priorities of frames of data of the other queues, an optical medium forming a digital data communication path among said processors, an output buffer memory configured to have a plurality of separate logical first in-first out (FIFO) memory regions for storing respectively the plurality of queues of framed data to be transmitted to the optical medium, and means for transmitting said framed data, stored in said logical FIFO memory regions of said output buffer memory, to said optical medium, each of the FIFO memory regions storing one of the queues:

a method of interfacing said system memory means and said optical medium, comprising the steps of;

accessing said optical medium upon a token capture in response to predetermined conditions, and in response,

controlling movement of framed data to be transmitted to said optical medium by

(a) transmitting said framed data from said system memory means to corresponding logical FIFOs in said output buffer memory, one queue at a time in order of priority, and

(b) transmitting said framed data stored in said logical FIFOs to said optical medium while data is incoming from said system memory means to said logical FIFOs.

42. The method of claim 41, wherein said logical FIFOs include transmit and receive logical FIFOs, the method including the additional steps of detecting the presence in a transmit FIFO of at least one full packet of said data, and in response, transferring said data to said optical medium.

43. The method of claim 42, including the additional steps of detecting the presence in said transmit FIFO of at least a predetermined amount of data, and in response, transferring said data to said optical medium when either at least a packet of said data or at least the predetermined amount of data is stored in the transmit FIFO.

44. The method of claim 41, wherein said logical FIFOs include transmit and receive logical FIFOs;

the method including the additional steps of detecting the presence in a transmit FIFO of at least a predetermined amount of data, and in response, transferring said data to said optical medium.

45. The method of claim 44, including the additional steps of

detecting data incoming from the medium to be stored in the system memory means;

transferring data from said optical medium to said receive FIFO;

detecting a predetermined amount of data stored in said receive FIFO from said optical medium; and

in response,

transferring said data from said receive FIFO to said system memory means.

46. For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet (tag) bit, a network controller, comprising:

a random access memory;

means for defining in said random access memory a buffer memory configured as a transmit FIFO;

means for transferring from said system memory means to said transmit FIFO successive frames of data demarked by said end of packet (tag) bits and forming a queue to be transmitted;

first detector means for detecting that at least one full frame of data is stored in said transmit FIFO;

second detector means for detecting that at least a predetermined amount of data is stored in said transmit FIFO; and

means responsive to at least one of said first and second detector means for transmitting the content of said transmit FIFO to a network;

wherein said transmit FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said transmit FIFO, and a SHADOW WRITE pointer pointing to the end of a full frame stored in said transmit FIFO, wherein said first detector means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.

47. For a network adapter including at least one processor and system memory means for storing packets of data arranged in frames having at least data bits and an end of packet (tag) bit, a network controller, comprising:

a random access memory;

means for defining in said random access memory a buffer memory configured as a receive FIFO;

means for storing in said receive FIFO incoming receive data packets demarked by said end of packet (tag) bits and forming a receive queue;

means for storing a receive data threshold value;

means for detecting that the content of said receive FIFO exceeds said receive data threshold value; and

means responsive to said detecting means for transferring data from said receive FIFO to said system memory means;

wherein said receive FIFO is defined by START and END pointers, and including READ and WRITE pointers, a SHADOW WRITE pointer pointing to the beginning of the latest frame being received in the receive FIFO, and a receive threshold value, wherein said receive data is transferred to said system memory means when said write pointer exceed said threshold value and when said receive data is to be flushed, the write pointer is replaced by the shadow write pointer.

48. For a Fiber Distributed Data Interface (FDDI) network having a plurality of processors, each including a system memory means for storing frames of data arranged in queues and having a plurality of different transmit priorities, and an optical medium forming a digital data communication path among said processors, a network controller, comprising:

first means implementing a timed token data protocol for accessing said optical medium;

a random access memory forming a buffer memory; and

second means for configuring in said random access memory a plurality of logical FIFOs for storing therein said queued frames of data having respectively said plurality of different transmit priorities;

means for controlling flow of said framed data to corresponding logical FIFOs in said buffer memory, said framed data flow controlling means including first means for controlling flow of said framed data, one queue at a time in order of priority, from said system memory means to corresponding logical FIFOs in said buffer memory, and second means for transmitting said framed data, stored in said logical FIFOs to said medium while data is incoming from said system memory means to said FIFOs in said buffer memory;

wherein each said logical FIFO is defined by START and END pointers and including a READ pointer and a WRITE pointer respectively for reading data to and writing data from said logical FIFO and a SHADOW WRITE pointer pointing to the end of a full frame stored in said logical FIFO, and wherein said data flow controlling means includes means for detecting when said SHADOW WRITE pointer exceeds said READ pointer.