Pattern synchronizing circuit

• US 5,210,754 A
• Filed: 06/04/1991
• Issued: 05/11/1993
• Est. Priority Date: 06/06/1990
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Akiyama, Noboru, Takahashi, Toshiro, Nakajima, Takayuki, Sotome, Tetsuo
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/710,522
• Time in Patent Office: 707 Days
• Field of Search: 370/100.1, 370/105.4, 370/106, 375/114, 375/116, 375/119, 340/146.2
• US Class Current: 370/514
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.

Claims

1. A pattern synchronizing circuit comprising:

pre-clock eliminating means for eliminating one clock pulse from a high-speed clock input thereto upon each application thereto of a pre-clock pulse eliminating signal;

clock dividing means for frequency dividing the high-speed clock output from said pre-clock eliminating means to 1/N;

demultiplexing means for sequentially demultiplexing consecutive bits of high-speed input data into N parallel low-speed sequences on N output lines in synchronization with said high-speed clock and said N sequences of low-speed data are output in synchronization with said frequency divided clock, N being an integer equal to or greater than 2;

post-clock pulse eliminating means, supplied with said frequency divided clock, for eliminating one pulse from said frequency divided clock upon each application thereto of a post-clock pulse eliminating signal and outputting an output clock;

reference pattern generating means for generating N parallel sequences of reference patterns, sequentially displaced apart in phase, in synchronization with the output clock of said post-clock pulse eliminating means;

N comparators, whereby an Nth sequence of low-speed data, composed of data of every Nth bit of N-bit data being sequentially demultiplexed by said demultiplexing means into N parallel sequences and output upon each occurrence of said frequency divided clock is compared with said N parallel sequences of reference patterns, each of said N comparators outputting an agreement or disagreement signal;

asynchronism detecting means for generating said post-clock pulse eliminating signal upon detecting that each of said N comparators has output said disagreement signal; and

synchronization setting means for detecting one of said N parallel sequences of reference patterns with which an Nth sequence of low-speed data is synchronized and for generating said pre-clock pulse eliminating signals of a number corresponding to a line position of said sequence of reference patterns synchronized with said Nth sequence of low-speed data, whereby line positions of said N parallel sequences of low-speed data are sequentially shifted by said corresponding number in said demultiplexing means so that said Nth sequence of low-speed data assumes the same line position as that of said synchronized reference pattern.

2. A pattern synchronizing circuit according to claim 1, wherein said synchronizing detecting means includes:

N hold means for holding predetermined logical states in response to disagreement signals from said N comparators; and

post-clock pulse eliminating signal generating means for generating said post-clock pulse eliminating signal and for resetting said N hold means when all of said N hold means enter said predetermined logical states.

3. A pattern synchronizing circuit according to claim 2, further comprising counter means for counting the number of said post-clock pulse eliminating signals and for applying said pre-clock pulse eliminating signals to said pre-clock eliminating means once when the count value of said counter means reaches a predetermined number.

4. A pattern synchronizing circuit according to claim 2, further comprising N-1 select means for selecting said Nth sequence of low-speed data and the other N-1 sequences of low-speed data, and wherein said Nth sequence of low-speed data and output data of said N-1 select means are provided to said N comparators and during a synchronizing operation each of said N-1 selects means selects and outputs said Nth sequence of low-speed data to a corresponding one of said N-1 comparators whereby N sequences, each identical to said Nth sequence of low-speed data, are compared by said N comparators with said N parallel sequences of reference patterns.

5. A pattern synchronizing circuit according to claim 1, wherein said synchronizing setting means includes:

synchronization detecting means, reset upon each application of said post-clock pulse eliminating signal, for counting the number of output clock pulses of said post-clock eliminating means and outputting a synchronization detecting signal when the count value reaches a predetermined value; and

pre-clock pulse eliminating signal generating means for responding to said synchronization detecting signal to output, as said pre-clock pulse eliminating signal said output clock pulses of said post-clock eliminating means by said corresponding number.

6. A pattern synchronizing circuit according to claim 5, wherein each of said reference patterns is a maximum length linear shift register sequence of a (2ⁿ -1)bit length and said predetermined value is equal to or greater than n, n being a positive integer.

7. A pattern synchronizing circuit according to claim 5, further comprising counter means for counting the number of said post-clock pulse eliminating signals and for applying said pre-clock pulse eliminating signals to said pre-clock eliminating means once when the count value of said counter means reaches a predetermined number.

8. A pattern synchronizing circuit according to claim 5, further comprising N-1 select means for selecting said Nth sequence of low-speed data and the outer N-1 sequences of low-speed data, and wherein said Nth sequence of low-speed data and output data of said N-1 select means are provided to said N comparators and during a synchronizing operation each of said N-1 select means selects and outputs said Nth sequence of low-speed data to a corresponding one of said N-1 comparators whereby N sequences, each identical to said Nth sequence of low-speed data, are compared by said N comparators with said N parallel sequences of reference patterns.

9. A pattern synchronizing circuit according to claim 1, further comprising counter means for counting the number of said post-clock pulse eliminating signals and for applying said pre-clock pulse eliminating signal to said pre-clock eliminating means once when the count value of said counter means reaches a predetermined number.

10. A pattern synchronizing circuit according to claim 9, wherein each of said reference patterns is a maximum length linear shift register sequence of a (2ⁿ -1) bit length and said predetermined number is an integer approximately equal to (2ⁿ -1)/N, n being a positive integer.

11. A pattern synchronizing circuit according to claim 1, further comprising N-1 select means for selecting said Nth sequence of low-speed data and the other N-1 sequences of low-speed data, and wherein said Nth sequence of low-speed data and output data of said N--1 select means are provided to said N comparators and during a synchronizing operation each of said N-1 select means selects and outputs said Nth sequence of low-speed data to a corresponding one of said N-1 comparators whereby N sequences, each identical to said Nth sequence of low-speed data, are compared by said N comparators with said N parallel sequences of reference patterns.