Memory address space determination using programmable limit registers with single-ended comparators

• US 5,210,850 A
• Filed: 06/15/1990
• Issued: 05/11/1993
• Est. Priority Date: 06/15/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Collins, Michael J., Kelly, Philip C.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US07/538,724
• Time in Patent Office: 1,061 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/246.7, 364/969.1, 395/425, 395/400, 371/19
• US Class Current: 710/220
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass

Abstract

An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

Claims

1. An apparatus for determining if a memory address value developed in a computer system is within a plurality of memory address regions, the computer system including a microprocessor, system memory, and a system memory address space comprising a predefined intermediate memory address value, the apparatus comprising:

means for generating a signal which indicates whether said developed memory address value is greater than the intermediate memory address value;

a first storing means for storing a first memory address value which serves as a first boundary of a first memory address region;

a second storing means for storing a second memory address value which serves as a first boundary of a second memory address region;

a third storing means for storing a third memory address value which serves as a first boundary of a third memory address region;

a first comparing means coupled to said first storing means for comparing said developed memory address value with said first memory address value, wherein said first comparing means only determines whether said developed memory address value is less than the memory address value stored in said first storing means and generates a first signal indicative thereof, said first indicating signal indicating that said developed memory address value resides in said first memory address region based only on whether said developed memory address value is less than said first memory address value stored in said first storing means;

a second comparing means coupled to said second storing means for comparing said developed memory address value with said second memory address value, wherein said second comparing means only determines whether said developed memory address value is greater than or equal to said second memory address value stored in said second storing means and generates a second signal indicative thereof, said second indicating signal indicating that said developed memory address value resides in said second memory address region based only on whether said developed memory address value is greater than or equal to said second memory address value stored in said second storing means; and

a third comparing means coupled to said third storing means for receiving said intermediate address indicating signal and for comparing said developed memory address value with said third memory address value, wherein said third comparing means determined whether said developed memory address value resides between the memory address value stored in said third storing means and the intermediate memory address value using only the third memory address value stored in said third storing means and said intermediate address indicating signal and generates a third signal indicative thereof, said third indicating signal indicating that said developed memory address value resides in said third memory address region if said developed memory address value resides between the memory address value stored in said third storing means and the intermediate memory address value.

2. The apparatus of claim 1, wherein said third storing means stores a memory address value greater than said intermediate memory address value.

3. The apparatus of claim 1, wherein each of said memory address regions has associated with it only one said memory address value storing means storing only one memory address value and only one said comparing means performing only one memory address value comparison.

4. The apparatus of claim 3, wherein said system memory address space comprises a lowest memory address and a highest memory address, the apparatus further comprising:

the first memory address region associated with said first storing means being located between said first memory address value stored in said first storing means and said lowest memory address; and

the second memory address region associated with said second storing means being located between said second memory address value stored in said second storing means and said highest memory address.

5. The apparatus of claim 3, wherein said computer system further includes cache memory and a cache controller,

wherein one of said memory address regions is designated as a cacheable memory address region such that said indicating signal generated by said comparing means associated with said memory address region designated as said cacheable memory address region indicates that said developed memory address value resides in said cacheable memory address region;

the apparatus further comprising;

means coupled to said cache controller for receiving said indicating signal from said comparing means associated with said memory address region designated as said cacheable memory address region and for generating a cacheable address signal to said cache controller which indicates whether said developed memory address value is located in said cacheable memory address region.

6. The apparatus of claim 5,

wherein one of said memory address regions is designated as a write protect memory address region such that said indicating signal generated by said comparing means associated with said memory address region designated as said write protect memory address region indicates that said developed memory address value resides in said write protect memory address region;

the apparatus further comprising;

indicating signal receiving means for receiving said indicating signal from said comparing means associated with said memory address region designated as said write protect memory address region and for generating a write protect signal to said cache controller which indicates whether said developed address is located in said write protect memory address region.

7. The apparatus of claim 5, further comprising an enabling bit, wherein when said enabling bit is cleared the system memory space is deemed cacheable and said indicating signal from said comparing means associated with said cacheable memory address region is ignored and when said enabling bit is set the system memory space, subject to exceptions provided by said indicating signal from said comparing means associated with sand cacheable memory address region, is deem non-cacheable, and said indicating signal from said comparing means associated with said cacheable memory address regions is enabled to designate cacheable address region in the system memory space.

8. The apparatus of claim 5, further comprising:

said receiving means further comprising an input for receiving a signal generated by external logic, wherein said external logic signal can force said cacheable address signal to indicate that a generated memory address value is a cacheable or non-cacheable address.

9. The apparatus of claim 1, wherein said first, second, and third storing means are programmable.

10. The apparatus of claim 9, wherein each of said memory address boundary value storing means stores a number of address bits representing a memory address value.

11. The apparatus of claim 1, wherein said third storing means stores a memory address value less than said intermediate memory address value.

12. An apparatus for determining if a memory address value developed in a computer system is within any of a plurality of memory address regions, the computer system having a given address space, the address space being divided into regions based on the beginning of the address space and a memory address value intermediate in the address space, the apparatus comprising:

means for performing an address decode of said developed memory address value to determine if said developed memory address value is greater than the intermediate memory address value and for producing an intermediate address decode signal indicative thereof;

a first storing means for storing a first memory address value associated with a first memory address region at the beginning of the address space;

a second storing means for storing a second memory address value associated with a second memory address region having one boundary at the intermediate memory address value;

a third storing means for storing a third memory address value associated with a third memory address region having one boundary at the intermediate memory address value;

a first comparing means for comparing the developed memory address with said first memory address value stored in said first storing means and determining if said developed memory address value is less than said stored first memory address value, said first comparing means generating a signal indicating whether the developed memory address value resides in said first address region based only on said comparison of the developed memory address value with said first memory address value stored in said first storing means;

a second comparing means for receiving said intermediate address decode signal and for comparing the developed memory address value with said second memory address value stored in said second storing means and for determining if said developed memory value is greater than said stored second memory address value and producing a second signal indicative thereof and for defeating operation of said determining if said intermediate address decode signal indicates that said developed memory address value is greater than said second memory address value, said second indicating signal indicating whether the developed memory address value resides in said second address region based only on said comparison of the developed memory address value with said second memory address value stored in said second storing means and said intermediate address decode signal; and

a third comparing means for receiving said intermediate address decode signal and for comparing the developed memory address value with said third memory address value stored in said third storing means and for determining if said developed memory address value is less than said stored third memory address value and producing a signal indicative thereof and for defeating operation of said determining if said intermediate address decode signal indicates that said developed memory address value is not greater than the intermediate address value, said third indicating signal indicating whether the developed memory address value resides in said third address region based only on said comparison of the developed memory address value with said third memory address value stored in said third storing means and said intermediate address decode signal.

13. The apparatus of claim 12, the computer system address space having a further division based on the end of the address space, the apparatus further comprising:

a fourth storing means for storing a fourth memory address value associated with the end of the address space; and

a fourth comparing means for comparing the developed memory address value with said fourth memory address value stored in said fourth storing means and for determining if said developed memory address value is greater than said stored fourth memory address value, said fourth comparing means generating a signal indicating whether the developed memory address value resides in said fourth address region based only on said comparison of the developed memory address value with said fourth memory address value stored in said fourth storing means.