Method for verifying a serializing function in a system including processors and a test system including processors for verifying the serializing function

• US 5,210,861 A
• Filed: 05/30/1990
• Issued: 05/11/1993
• Est. Priority Date: 05/30/1989
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shimoda, Akira
• Primary Examiner(s): Beausoliel, Robert W.
• Assistant Examiner(s): HUA, LY
• Application Number:
  US07/530,327
• Time in Patent Office: 1,077 Days
• Field of Search: 364/200, 364/900, 364/228.1, 364/242.91, 364/265.6, 364/226.1, 364/267 A, 364/267.7, 364/269, 364/271, 364/271.3, 364/271.2, 364/931.43 , 364/931.48, 364/950, 364/950.3, 364/950.4, 364/944.6, 364/445.4, 364/945.7, 371/15.1, 371/16.1
• US Class Current: 714/32
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00

Abstract

A method for verifying a serializing function in a system including a plurality of processors and a test system including processors for verifying the serializing function. Each processor executes a verifying processing including the steps of: synchronizing an execution status of its own processor with an execution status of another processor; delaying an initiation of a next execution for a predetermined changeable period; issuing and executing a serializing instruction indicating a set of data read and write processings; and verifying whether the serializing instruction is normally executed or not. By controlling a timing of the execution of the serializing instruction at random between each processor, it is possible to verify normality of the serializing function satisfactorily and in a short time, while specifying whether cause for a fault occurring in the entire system is due to the serializing function or not.

Claims

1. A method for verifying a serializing function in a system having a plurality of processors in which data from predetermined areas in a common storage are transferred to an internal storage provided in a first processor and the data is accessed by the plurality of processors, said method comprising the steps of:

(a) synchronizing, in the first processor, an execution status of the processor with an execution status of a second processor;

(b) delaying execution in the first processor for a predetermined changeable period selected at random by the first processor;

(c) issuing and executing a serializing instruction in the first processor indicating a set of data read and write processings; and

(d) verifying whether the serializing instruction in the first processor is executed without an error indication.

2. A method as set forth in claim 1 further comprising the step of (e) initializing the internal storage in the first processor and the common storage to control repetition of each step starting from step (a), whereby the timing of the execution of said serializing instruction is controlled repeatedly between each processor.

3. A method as set forth in claim 2, wherein step (c) comprises the steps of (c1) executing said serializing instruction to read a first area set for the first processor and write a given data in the first area, (c2) reading a second area set for the second processor to determine a write status of data by the second processor, and (c3) repeatedly reading the second area to determine the write status where the second area is not in the write status, and step (d) comprises the steps of (d1) monitoring the execution status of the second processor and d(2) indicating occurrence of an error when the second processor is still executing step (c3) after a lapse of predetermined time.

4. A method as set forth in claim 3, wherein step (e) includes the step of filling the internal storage in the first processor with data other than data corresponding to areas for use of verification of the serializing function.

5. A method for verifying a serializing function in a system having a plurality of processors in which data from predetermined areas in a common storage are transferred to an internal storage provided in a first processor and the data is accessed by the plurality of processors, said method verifying proper execution of the serializing function of inhibiting access to the data by a second processor during execution of a serializing instruction indicating a set of data read and write processings, said method comprising the steps of:

(a) synchronizing, in the first processor, an execution status of the processor with an execution status of another processor;

(b) delaying execution in the first processor for a predetermined changeable period selected at random by the first processor;

(c) executing said serializing instruction in the first processor to read a first area set for the first processor and write a given data in the first area, then reading a second area set for the second processor to determine a write status of data by the second processor, and repeatedly reading the second area to determine the write status where the second area is in a nonwrite status;

(d) monitoring the execution status of the second processor and, where the second processor is still reading the second area in step (c) after a lapse of predetermined time, indicating occurrence of an error; and

(e) initializing the internal storage and the common storage to control repetition of each step from said synchronizing step (a).

6. A test system including a plurality of processors for verifying a serializing function, in which data of predetermined areas in a common storage are transferred to an internal storage provided in a first processor and the data is accessed by the plurality of processors, each processor comprising:

synchronizing means for synchronizing an execution status of the first processor with an execution status of a second processor;

delay means for delaying execution by the first processor for a predetermined changeable period selected at random after completion of said synchronizing processing by said synchronizing means;

serializing means for issuing and executing a serializing instruction indicating a set of data read and write processings after the delaying by said delay means is completed; and

verifying means for verifying whether the serializing instruction executed by said synchronizing means is executed without an error indication.

7. A test system as set forth in claim 6, further comprising initializing means for initializing the internal storage and the common storage.

8. A test system as set forth in claim 7, wherein the serializing means comprises means for executing said serializing instruction after completion of said delaying processing to read a first area set for the first processor and write a given data in the first area, then reading a second area set for the second processor to determine a write status of data by the second processor, and repeatedly reading the second area to determine the write status where the second area is in a nonwrite status, and the verifying means comprises means for monitoring the execution status of the second processor and indicating occurrence of an error when the second processor is still reading the second area after a lapse of predetermined time.

9. A test system as set forth in claim 8, wherein the initializing means includes means for filling the internal storage with data other than data corresponding to areas for use of verification of the serializing function.

10. A test system having a plurality of processors in which data of predetermined areas in a common storage are transferred to an internal storage provided in a first processor the data is accessed by the plurality of processors, said test system verifying normality of a serializing function of inhibiting access to the data by a second processor during execution of a serializing instruction indicating a set of data read and write processings, said processor comprising:

synchronizing means for synchronizing an execution status of the first processor with an execution status of the second processor;

delay means for delaying execution by the first processor for a predetermined changeable period selected at random after completion of processing by said synchronizing means;

serializing means for executing said serializing instruction after completion of said delaying means to read a first area set for the first processor and write a given data in the first area, reading a second area set for the second processor to determine a write status of data by the second processor, and repeatedly reading the second area to determine the write status where the second area is in a non-write status;

error detection means for monitoring an execution status of the second processor and, where the second processor is still reading the second area to determine the write status after a lapse of predetermined time, indicating occurrence of an error; and

initializing means for initializing the internal storage and the common storage to control repetition of each processing from the synchronizing initially performed by said synchronizing means.

11. A method of verifying, in a first processor, serialization of access to a common storage in a multiprocessor system, comprising the steps of:

(a) synchronizing execution of the first processor with execution of a second processor;

(b) delaying execution by the first processor of a serializing instruction by a randomly variable amount of time;

(c) executing the serializing instruction in the first processor;

(d) verifying that serialization was obtained by the serializing instruction; and

(e) repeating steps (a) through (e) so that step (b) delays execution by different amounts of time.

12. A test system for verifying serialization of access to a common storage in a multiprocessor system, said test system comprising:

a plurality of processors, a first processor comprising;

synchronizing means for synchronizing execution of the first processor with execution of a second processor;

delay means for delaying, after synchronization by said synchronization means, execution by the first processor of a serializing instruction by a randomly variable amount of time;

serializing means for executing the serializing instruction in the first processor after the delaying of execution by said delay means;

verifying means for verifying serializing by the serializing instruction executed by said serializing means; and

repeat means for repeating the processing performed by said synchronizing means, said delay means, said serializing means, and said verifying means so that said delay means delays execution by different amounts of time.