Method and apparatus for memory retry

• US 5,210,867 A
• Filed: 10/05/1990
• Issued: 05/11/1993
• Est. Priority Date: 10/05/1990
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Pence, Michelle A., Barlow, George J., Bowden, Raymond D. III
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/593,182
• Time in Patent Office: 949 Days
• Field of Search: 371/12, 371/13, 371/32, 371/33, 364/267.3, 364/285.2, 395/575
• US Class Current: 714/17
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying

Abstract

Memory retry logic to improve the resilience of system memory operations with respect to system errors or faults which prevent a memory read operation from being completed on a first attempt by allowing the memory to retry the operation once. The memory retry logic detects the occurrence of an improper response from the system element requesting a memory read operation when attempting to initiate the system bus operation for reading the data from memory to the requesting element and, if an improper response indicating that the requesting element is not accepting the bus operation request is detected, stores the memory operation request and the requested data and retries the data transmission on the next available bus cycle. If the memory receives an improper response of a specified type during a bus operation of a memory burst, the memory will terminate the operation and proceed to the next requested operation.

Claims

1. In a data processing system having a memory for storing and providing data, system elements for operating on the data, and a system bus connected between the memory and the system elements, each bus transfer including a request for a bus transfer operation and a response to a bus transfer operation and either a request for memory data or the requested data, each system element including a means for generating requests for data form the memory, the memory including a memory control means including a bus control means connected to the system bus for generating and providing on the system bus requests for bus transfers and for responding to requests provided on the system bus by system elements for bus transfers, the memory including a memory operation retry means, comprising:

memory timing means connected from the bus control means and responsive to a memory request on the system bus for generating a bus transfer signal for indicating the occurrence of a request for a bus transfer of memory data to a system element requesting memory data,

the bus control means connected from the system bus and responsive to the system element responses on the system bus to memory requests for bus transfers for asserting an improper response signal when the memory bus control means has received an improper response to a memory request for a bus transfer, and

retry means connected from the memory timing means and the memory bus control means and responsive to the improper response signal and to the bus transfer signal when the memory has asserted a request for a bus transfer of the memory data for generating a retry signal, wherein

the memory control means is connected form the retry means and is responsive to the retry signal to latch the present memory request and the corresponding requested data in the memory, and

to attempt to retry to transmit the requested data to the requesting system element.

2. The memory operation retry means of claim 1, further comprising:

retry latch means connected from the retry means to store the retry signal, and wherein

the retry means is responsive to the occurrence of a second occurrence of the retry signal during the attempt to retry to transmit the requested data for asserting an end cycle signal,

the memory control means is connected from the retry means and responsive to the end cycle signal for terminating the memory operation.

3. The memory operation retry means of claim 1, wherein the requests for data asserted by the system elements includes requests for bursts of a fixed number of words of memory data, further comprising:

in the bus control means, a means for generating a burst signal indicating that a present request for memory data is a request for a burst operation, and

in the memory timing means, means connected from the burst signal output of the bus control means and responsive to the burst signal for indicating the transmission of data in response to a burst request, and

burst termination means connected from the bus control means and the timing means and responsive to a request for a bus transfer operation by the memory, to the burst signal and to an improper response signal during a burst transmission for asserting an end burst signal, wherein

the memory control means is responsive to the end burst signal to terminate the memory burst operation.

4. In a data processing system having a memory for storing and providing data, system elements for operating on the data, and a system bus connected between the memory and the system elements for performing bus transfers between the memory and the system elements, each bus transfer including a request for a bus transfer operation and a response to a bus transfer operation and either a request for memory data or the requested data, each system element including memory control means being responsive to the data requests for providing the requested data, and each system element and the memory control means including a bus control means for asserting requests for bus transfers and responding to requests for bus transfers, a method for improving the resiliency of the memory to improper responses from system elements, comprising the steps of:

in a memory timing means connected form the memory bus control means and responsive to a bus operation request provided on this system bus for a transfer memory data to a system element, generating a bus request signal indicating the occurrence of a request for a bus transfer of memory data to a system element requesting memory data,

in the bus control means connected from the system bus and responsive to the system element responses to memory requests for bus transfers, generating an improper response signal when the memory bus control means has received an improper response to a memory request for a bus transfer, and

in a retry means connected from the memory timing means and the memory bus control means and responsive at the bus request signal and the improper response signal, generating a memory retry signal in responsive to the improper response signal when the memory has asserted a request for a bus transfer of the memory data, and

in the memory control means connected from the retry means and responsive to the retry signal, latching the present memory request and the corresponding requested data in the memory, and

attempting to retry to transmit the requested data to the requesting system element.

5. The memory operation resiliency method of claim 4, further comprising the steps of:

in a retry latch means connected from the retry means and responsive to the retry signal,

storing the retry signal, and

responsive to the occurrence of a second generation of the retry signal during the attempt to retry to transmit the requested data, asserting an end cycle signal, and

in the memory control means connected from the end cycle signal output of the retry means and responsive to the end cycle signal, terminating the memory operation.

6. The memory operation resiliency method of claim 4, wherein the requests for data generated by the system elements includes requests for bursts of a fixed number of words of memory data, further comprising the steps of:

in the bus control means and responsive to requests for bursts of memory data, generating a burst signal indicating that the present request for memory data is a request for a burst operation, and

in the memory timing means connected from the burst signal output of the bus control means, generating a burst transmission signal indicating the transmission of data in response to a burst request, and

in a burst termination means connected from the bus control means and the timing means and responsive to the improper response signal and the burst transmission signal during a burst transmission, asserting an end burst signal, and

in the memory control means connected from the end burst signal output of the burst termination means and responsive to the end burst signal, terminating the memory burst operation.

7. In a data processing system having a memory for storing and providing data, system elements for operating on the data, and a system bus connected between the memory and the system elements for bus transfers between the memory and the system elements, each bus transfer including a request for a bus transfer operation and a response to a bus transfer operation and either a request for memory data or the requested data, each system element including a system element control means for generating requests for data from the memory, the memory including a memory control means connected from the system bus and responsive to the data requests for providing the requested data, and each system element and the memory control means including a bus control means connected to the system bus and respectively to the system element control means and to the memory control means for generating requests for bus transfers and responding to requests for bus transfers, a method for improving the resiliency of the memory to improper responses from the system elements, comprising the steps of:

in a memory timing means connected from the memory bus control means and responsive to a bus request on the system bus, generating

a bus transfer signal having a first state indicating that the memory is transmitting the requested data and a second state indicating that the memory is not transmitting the requested data,

in the bus control means and responsive to the system element responses to memory requests for bus transfers, generating an improper response signal when the memory bus control means has received an improper response to a memory request for a bus transfer, and

in a retry means connected form the memory timing means and the memory bus control means and responsive to the improper response signal and to the bus transfer signal when the timing signal is asserted in the second state, generating a retry signal, and

in the memory control means and connected from the retry signal output of the retry means and responsive to the retry signal, latching the present memory request and the corresponding requested data in the memory, and

attempting to retry to transmit the requested data to the requesting system element.

8. The memory operation resiliency method of claim 7, further

in a retry latch means connected from the retry signal output of the retry means and responsive to the retry signal,

storing the retry signal, and

responsive to the occurrence of a second generation of the retry signal during the attempt to retry to transmit the requested data, generating an end cycle signal, and

in the memory control means and connected form the end cycle signal output of the retry latch means and responsive to the end cycle signal, terminating the memory operation.

9. The memory operation resiliency means of claim 7, wherein the requests for data asserted by the system elements include requests for bursts a fixed number of words of memory data, further comprising the steps of:

in the bus control means and responsive to a request for a burst operation, generating a burst signal indicating that a present request for memory data is a request for a burst operation, and

in a burst termination means connected from the improper response output and the bust signal output of the bus control means and responsive to the improper response signal when the burst signal and the second timing signal is asserted in the first state, generating an end burst signal, and

in the memory control means and connected form the end burst signal output of the burst termination means and responsive to the end burst signal, terminating the memory burst operation.