Linearized and delay compensated all CMOS VCO

• US 5,212,459 A
• Filed: 10/13/1992
• Issued: 05/18/1993
• Est. Priority Date: 11/12/1991
• Status: Expired due to Term

• Current Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Original Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Inventors: Robertson, Craig, Lam, Kwai-Kwong, Ueda, Shunsaku
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/960,534
• Time in Patent Office: 217 Days
• Field of Search: 331/111, 331/143, 331/177 R
• US Class Current: 331/111
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence

Abstract

The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.

Claims

1. A method of delay compensating the generation of a signal having two states, said method comprising the steps of:

generating a first ramping signal responsive to an input signal, said ramping signal having an actual amplitude range and an ideal amplitude range;

comparing said first ramping signal to a threshold signal for determining a threshold crossing of said ramping signal with said threshold signal;

producing an output signal having at least two states, said output signal changing states dependent on said threshold crossing;

generating a second ramping signal responsive to said output signal, said second ramping signal mirroring said first ramping signal;

determining an amplitude level of said second ramping signal when said output signal changes state, said amplitude level of said second ramping signal corresponding to a delay between said first ramping signal crossing said threshold signal and a change in said states of said output signal; and

adding said amplitude level of said second ramping signal to a reference signal for modifying said threshold signal, said threshold signal minimizing a difference between said actual amplitude range and said ideal amplitude range of said first ramping signal.