TDM expansion bus
First Claim
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1. Network module apparatus for receiving an input series time division multiplexed (TDM) digital signal and for transmitting information contained therein onto a bus and for receiving information from the bus and generating an output serial TDM signal, which apparatus comprises:
- means, responsive to the input TDM signal, for generating a receive clock signal (CLKR) having a clock rate which is substantially equal to a data information clock rate of the input serial TDM signal and for driving the receive clock signal on a receive clock pathway on the bus;
means, responsive to the input TDM signal, for generating a serial receive data signal (SERR) and for driving the receive data signal on a receive data pathway on the bus;
means, responsive to the input TDM signal, for generating receive synchronization and framing signals (FSYNCR and MSYNCR) and for driving the receive synchronization and framing signals on receive synchronization and framing pathways on the bus; and
means, responsive to;
(a) a transmit clock signal (CLKT) applied thereto over a transmit clock pathway on the bus, (b) transmit synchronization and framing signals (FSYNCT and MSYNCT) applied thereto over transmit synchronization and framing pathways on the bus, and (c) a serial transmit data signal (SERT) applied thereto over a transmit data pathway on the bus, for generating the output TDM signal.
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Abstract
TDM bus and, in particular, a PCM Expansion Bus (PEB): (a) which permits a multiplicity of apparatus to monitor a TDM signal simultaneously and (b) wherein various timing and control signals are provided in a manner that minimizes the hardware needed by the apparatus for identifying, i.e., decoding, various channels in the TDM signal for accessing and inserting information therein.
12 Citations
17 Claims
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1. Network module apparatus for receiving an input series time division multiplexed (TDM) digital signal and for transmitting information contained therein onto a bus and for receiving information from the bus and generating an output serial TDM signal, which apparatus comprises:
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means, responsive to the input TDM signal, for generating a receive clock signal (CLKR) having a clock rate which is substantially equal to a data information clock rate of the input serial TDM signal and for driving the receive clock signal on a receive clock pathway on the bus; means, responsive to the input TDM signal, for generating a serial receive data signal (SERR) and for driving the receive data signal on a receive data pathway on the bus; means, responsive to the input TDM signal, for generating receive synchronization and framing signals (FSYNCR and MSYNCR) and for driving the receive synchronization and framing signals on receive synchronization and framing pathways on the bus; and means, responsive to;
(a) a transmit clock signal (CLKT) applied thereto over a transmit clock pathway on the bus, (b) transmit synchronization and framing signals (FSYNCT and MSYNCT) applied thereto over transmit synchronization and framing pathways on the bus, and (c) a serial transmit data signal (SERT) applied thereto over a transmit data pathway on the bus, for generating the output TDM signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. Network module apparatus for receiving at least one input analog signal and at least one input analog signaling signal and for transmitting information contained therein onto a bus and for receiving information from the bus and generating at least one output analog signal and at least one output analog signaling signal, which apparatus comprises:
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means, responsive to the at least one input analog signal and to the at least one input analog signaling signal, for generating a serial receive data signal (SERR) and for driving the receive data signal on a receive data pathway on the bus; means for generating a receive clock signal (CLKR) having a clock rate which is substantially equal to a data information clock rate of the receive data signal and for driving the receive clock signal on a receive clock pathway on the bus; means for generating receive synchronization and framing signals (FSYNR and MSYNCR) and for driving the receive synchronization and framing signals on receive synchronization and framing pathways on the bus; and means, responsive to;
(a) a transmit clock signal (CLKT) applied thereto over a transmit clock pathway on the bus, (b) transmit synchronization and framing signals (FSYNCT and MSYNCT) applied thereto over transmit synchronization and framing pathways on the bus, and (c) a transmit data signal (SERT) applied thereto over a transmit data pathway on the bus, for generating the at least one output analog signal and the at least one output analog signaling signal. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification