Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation

• US 5,212,777 A
• Filed: 11/17/1989
• Issued: 05/18/1993
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M., Balmer, Keith, Gove, Robert J., Ing-Simmons, Nicholas K.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): GECKIL, MEHMET B
• Application Number:
  US07/437,858
• Time in Patent Office: 1,278 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/375, 395/325, 395/425
• US Class Current: 712/229
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

Claims

1. A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a multiple instruction multiple data (MIMD) mode comprising:

a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode;

a plurality of processors, each processors having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories, said plurality of memories including at least one data memory corresponding to each of said processors and an instruction memory corresponding to each of said processors;

a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said plurality of memories, said switch matrix including

a set of first links connected to said memories,

a set of second links connected to said data ports of said processors,

a third link having a plurality of sections equal in number to the number of said processors, each section connected to said instruction port of a corresponding one of said processors,

a plurality of buffers disposed between adjacent sections of said third link connecting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode, and splitting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode, and

a plurality of crosspoints disposed at intersections between said first links and said second links and at intersections between said first links and said sections of said third link, said crosspoints individually operating to connect said first and second links permitting said data port of a processors to access a memory, and to connect said first links and said third link permitting said instruction port of a processor to receive an instruction from an instruction memory,

said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said third link connected to said instruction port of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection,

said plurality of crosspoints including a set of second crosspoints disposed at the intersection of said section of said first link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode;

whereby said instruction port of each processor is connected to said instruction memory corresponding to said predetermined first processor in the single instruction multiple data (SIMD) mode via said first crosspoint, said sections of said third link and said buffers, and said instruction port of each processor is connected to said corresponding instruction memory in the multiple instruction multiple data (MIMD) mode via said corresponding second crosspoint and said corresponding section of said third link.

2. The multi-processor system claimed in claim 1, further comprising:

a communications bus permanently interconnecting all of said processors, said communication bus for coordinating change from the SIMD and MIMD modes.

3. The multi-processor system claimed in claim 2, wherein at least a portion of one of said memories is a parameter store memory storing a plurality of parameters and said communications bus includes circuitry for exchanging signals which specifies certain parameters stored in said parameter store memory.

4. The multi-processor system claimed in claim 2, wherein said parameters are stored in and retrieved from said parameter store memory via said switch matrix.

5. The multi-processor system claimed in claim 1, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said third link in the single instruction multiple data (SIMD) mode only said program counter of said predetermined first processor accesses said instruction memory corresponding to said predetermined first processor.

6. The multi-processor system claimed in claim 5, further comprising:

an external memory for storing instructions for each of said processors;

each instruction memory stores only a portion of the instructions for the corresponding processor; and

each processor further includes

a cache logic circuit connected to said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory,

said cache logic circuit requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode,

said cache logic circuit of each processor except said predetermined first processor disabled when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode, and

said cache logic circuit of said predetermined first processor requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode.

7. The multi-processor system claimed in claim 1, wherein:

said switch matrix wherein

said plurality of crosspoints including a set of third crosspoints disposed at the intersection of said first links connected to said instruction memories and said second links connected to said data ports of said plurality of processors, said set of third crosspoints disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode;

whereby access to said instruction memories via said data ports of said plurality of processors is prohibited when in the single instruction multiple data (SIMD) mode and permitted when in the multiple instruction multiple data (MIMD) mode.

8. The multi-processor system claimed in claim 1, wherein:

said SIMD/MIMD mode register stores therein an indication of either the single instruction multiple data (SIMD) mode of the multiple instruction multiple data (MIMD) mode for each of said plurality of processors;

said switch matrix wherein

said buffers connect adjacent sections of said third link in a serial chain from a first processor through to a last processor, each of said plurality of buffers connecting said adjacent sections of said third link only when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode for a corresponding processor, and splitting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor,

said second crosspoints being disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode for a corresponding processor and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor;

wherein some of said plurality of processors may operate in the multiple instruction multiple data (MIMD) mode and while serial chains of processors operate in the single instruction multiple data (SIMD) mode, said instruction port of each processor in a serial chain of processors in the single instruction multiple data (SIMD) mode being connected to said instruction memory corresponding to a first processor in the serial chain, and said instruction port of each processor in the multiple instruction multiple data (MIMD) mode being connected to said corresponding instruction memory.

9. The multi-processor system claimed in claim 8, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said third link in the single instruction multiple data (SIMD) mode only said program counter of the first processor in a serial chain accesses said its corresponding instruction memory.

10. The multi-processor system claimed in claim 8, wherein:

said switch matrix wherein

said plurality of crosspoints including a set of third crosspoints disposed at the intersection of said first links connected to said instruction memories and said second links connected to said data ports of said plurality of processors, said set of third crosspoints disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode for a corresponding processor and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode the corresponding processor;

whereby access to said instruction memories via said data ports of any of said plurality of processors is prohibited when said processor is in the single instruction multiple data (SIMD) mode and permitted when said processor is in the multiple instruction multiple data (MIMD) mode.

11. A multi-processor system operable in either a single instruction multiple data (SIMD) mode or in a multiple instruction multiple instruction multiple data (MIMD) mode for each of said plurality of processors:

a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode of the multiple instruction multiple data (MIMD) mode for each of said plurality of processors;

a plurality of processors, each processors having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;

a plurality of memories, said plurality of memories including at least one data memory corresponding to each of said processors and an instruction memory corresponding to each of said processors;

a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said plurality of memories, said switch matrix including

a set of first links connected to said memories,

a set of second links connected to said data ports of said processors,

a third link having a plurality of sections equal in number to the number of said processors, each section connected to said instruction port of a corresponding one of said processors,

a plurality of buffers disposed between adjacent sections of said third link forming a serial chain from a first processor to a last processor, each buffer connecting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode for a corresponding processor, and splitting said adjacent sections of said third link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode for the corresponding processor, and

a plurality of crosspoints disposed at intersections between said first links and said second links and at intersections between said first links and said sections of said third link, said crosspoints individually operating to connect said first and second links permitting said data port of a processors to access a memory, and to connect said first links and said third link permitting said instruction port of a processor to receive an instruction from an instruction memory,

said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said third link connected to said instruction port of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection,

said plurality of crosspoints including a set of second crosspoints disposed at the intersection of said section of said first link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode,

said plurality of crosspoints including a set of third crosspoints disposed at the intersection of said first links connected to said instruction memories and said second links connected to said data ports of said plurality of processors, said set of third crosspoints disabled to prohibit connection when said SIMD/MIND register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIND) mode;

whereby said instruction port of each processor is connected to said instruction memory corresponding to a first processor in a serial chain in the single instruction multiple data (SIMD) mode, said instruction port of each processor in the multiple instruction multiple data (MIMD) mode is connected to said corresponding instruction memory, and access to said instruction memories via said data ports of said plurality of processors is prohibited when the corresponding processor is in the single instruction multiple data (SIMD) mode and permitted when the corresponding processor is in the multiple instruction multiple data (MIMD) mode.

12. The multi-processor system claimed in claim 11, further comprising:

a communications bus permanently interconnecting all of said processors, said communication bus for coordinating change from the SIMD and MIMD modes.

13. The multi-processor system claimed in claim 12, wherein:

at least a portion of one of said memories is a parameter store memory storing a plurality of parameters; and

said communications bus includes circuitry for exchanging signals which specifies certain parameters stored in said parameter store memory.

14. The multi-processor system claimed in claim 12, wherein:

said parameters are stored in and retrieved from said parameter store memory via said switch matrix.

15. The multi-processor system claimed in claim 12, further comprising:

an external memory for storing instructions for each of said processors;

each instruction memory stores only a portion of the instructions for the corresponding processor; and

each processor further includes

a cache logic circuit connected to said program counter for determining if the instruction corresponding to the address stored in said program counter is stored in said corresponding instruction memory,

said cache logic circuit requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory when said SIMD/MIMD register indicates said processor is in the multiple instruction multiple data (MIMD) mode,

said cache logic circuit of each processor not a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode being disabled, and

said cache logic circuit of a first processor of a serial chain of processors in the single instruction multiple data (SIMD) mode requesting the instruction corresponding to the address stored in said program counter from said external memory if the instruction is not stored in said corresponding instruction memory.

16. The multi-processor system claimed in claim 11, wherein:

each processor includes

a program counter having stored therein an address of a next instruction, and

an instruction fetch circuit for supplying to said instruction port said address stored in said program counter for fetching an instruction stored at said address; and

said switch matrix wherein

said buffers pass signals unidirectionally whereby when said buffers connect said adjacent sections of said third link in the single instruction multiple data (SIMD) mode only said program counter of a first processor in a serial chain of processors in the single instruction multiple data (SIMD) mode accesses its corresponding instruction memory.