System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory

• US 5,212,780 A
• Filed: 05/09/1988
• Issued: 05/18/1993
• Est. Priority Date: 05/09/1988
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Mitra, Sumit K., Padgaonkar, Ajay J.
• Primary Examiner(s): Anderson, Lawrence E.
• Assistant Examiner(s): Ellis, Richard Lee
• Application Number:
  US07/191,983
• Time in Patent Office: 1,835 Days
• Field of Search: 364/200, 364/900, 365/230.08, 365/230.06, 365/189.04, 365/230.04, 365/230.09, 395/800, 395/425
• US Class Current: 365/230.04
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.

Claims

1. An electronic processor in which data is cyclically processed, comprising:

a semiconductor memory arranged and adapted to be read from and written to, including

an array of memory cells arranged in rows and columns identifying memory locations of said semiconductor memory,

each of said memory locations having a unique address,

said array divided into a first half containing memory locations with even numbered addresses and a second half containing memory locations with odd numbered addresses,

signal generating means electrically connected to said semiconductor memory for generating electrical shift signals to increment the addresses of said memory locations through a sequence of consecutively higher numbered addresses,

selecting means for selecting an address designating a memory location from among the memory locations from which data is to be read,

access means responsive to the selection of an address for reading data from the memory location designated by said selected address in one of said first and second halves during a predetermined instruction processing cycle of said electronic processor, and

shift means responsive to an electrical shift signal generated by said signal generating means in response to the reading of data by said access means from said designated memory location for automatically writing data read from said designated memory location into the memory location in the other of said first and second halves of said array designated by the next sequentially higher address relative to said selected address during the same said predetermined instruction processing cycle.

2. A semiconductor memory, comprising:

a first array of rows and columns encompassing all even numbered memory address locations,

a second array of rows and columns encompassing all odd numbered memory address locations,

means for reading data from a selected address location in a row of one of said first and second arrays during a predetermined cycle of operation of said memory,

means for writing the data read from the selected address location into an address location in a row in the other of said first and second arrays, and

means responsive to the reading of data from said selected address location for automatically incrementing the address of said memory to cause said writing means to write the same data read from said selected address location into the next sequentially higher address location of said other of said first and second arrays during a single predetermined instruction cycle of said memory operation in which said reading of data occurred.

3. The method of claim 2, further including:

means for causing the data reading means to select the address location in the next row for the next readout of data after the data in the last address location of a row has been read.

4. A method for transferring data between address locations of a semiconductor memory, comprising:

partitioning said memory into first and second halves one of which contains all odd numbered address locations and the other of which contains all even numbered address locations of the memory,

reading data from a selected address location in one of said halves during an instruction cycle of operation, and

incrementing the addresses of said memory such that the same data which was read from the selected address location is written into the next sequentially higher address location of said memory in the other of said halves during a single instruction cycle of operation in which both reading from and writing into the respective halves of said memory takes place.