Programmable DMA controller

• US 5,212,795 A
• Filed: 02/10/1992
• Issued: 05/18/1993
• Est. Priority Date: 10/11/1988
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Hendry, David F.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US07/833,636
• Time in Patent Office: 463 Days
• Field of Search: 395/725, 395/425, 395/325, 395/800
• US Class Current: 710/28
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Claims

1. In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of said I/O devices to said memory, a direct memory access (DMA) controller for regulating access of each of said I/O devices to said bus, said DMA controller comprising:

global register means comprising;

priority register means for storing priority parameters for each of said I/O devices, said parameters corresponding to relative priorities accorded to simultaneously pending requests by at least some of said plural I/O devices for access to said bus,

interrupt register means for storing requests for access to said bus from respective ones of said I/O devices,

resolver means for determining from said priority register means and said interrupt register means one of said I/O devices to have access to said bus and for transmitting an acknowledgment to said one I/O device enabling said device to communicate with said memory on said bus;

channel register means comprising;

pointer register means for storing addresses of locations in said memory for communication with said one I/O device via said bus,

sequence register means for storing an address of a location in said memory containing a channel program instruction which is to be executed next;

arithmetic logic unit (ALU) means comprising;

means for one of incrementing and decrementing addresses stored in said pointer register means in accordance with a corresponding channel program instruction,

means for computing the next address to be stored in said sequence register means in accordance with a corresponding channel program instruction,

means for computing an initial contents of each of said register means in said channel register means in accordance with a corresponding channel program instruction;

said memory containing a sequence of channel program instructions for each of said channels at locations in said memory whose addresses are sequentially stored in said sequence register means, said instructions comprising means for defining;

a set up operation wherein the contents of each of said registers in said channel register means is initialized in accordance with said initial contents computed by said ALU means,

an access operation wherein data is transferred on said bus between a location in said memory whose address is currently stored in said pointer register means and said one I/O device enabled by said resolver means.

2. The DMA controller of claim 1 wherein said channel register means further comprise:

channel status register means for storing a data count corresponding to a data block size to be transferred in the corresponding channel, and

counter register means for storing a repeat count of the number of times an access operation is to be repeated in a corresponding channel to complete a corresponding channel program, wherein the contents of said channel status register means and said counter register means is initialized in accordance with said sequence of program instructions corresponding to said set up operation.

3. The DMA controller of claim 2 further comprising means for causing said DMA controller to relinquish access to said bus whenever one of:

the amount of data transferred on said bus during said access operation equals the data count stored in said channel status register, and

the access instruction has been executed repeatedly a number of times equal to said repeat count stored in said counter register means.

4. The DMA controller of claim 1 wherein a central processing unit (CPU) is connected to said bus, said DMA controller further comprising:

means for asserting a bus hold request to said CPU whenever said resolver means selects one of said I/O devices for access to said bus, and

wherein said CPU comprises means for enabling said DMA controller to control access to said bus by transmitting a bus hold acknowledgment to said DMA controller.

5. The DMA controller of claim 4 further comprising:

burst register means for storing a minimum amount of time that said DMA controller controls access to said bus upon being enabled by said CPU; and

means for ignoring control signals from said CPU removing access to said bus from said DMA controller.

6. The DMA controller of claim 1 wherein one of said I/O devices comprises another DMA controller which is a slave to said DMA controller.

7. The DMA controller of claim 1 wherein said global register means further comprise:

bandwidth register means for defining for each I/O device the amount of time that it is permitted to have access to said bus relative to the amount of time that it does not have access to said bus, and

means for terminating the access of said one I/O device upon expiration of said amount of time,

wherein the contents of said bandwidth register is initialized in accordance with said sequence of instructions corresponding to said set up operation.

8. In a direct memory access controller for a data system having a memory, plural input/output (I/O) devices and a bus connecting each of said I/O devices to said memory, the direct memory access (DMA) controller for regulating access of each of said I/O devices to said bus, the improvement comprising:

global register means comprising;

priority register means for storing priority parameters for each of said I/O devices, said parameters corresponding to relative priorities accorded to simultaneously pending requests by at least some of said plural I/O devices for access to said bus,

interrupt register means for storing requests for access to said bus from respective ones of said I/O devices,

resolver means for determining from said priority register means and said interrupt register means one of said I/O devices to have access to said bus and for transmitting an acknowledgment to said one I/O device enabling said device to communicate data on said bus;

channel register means comprising;

pointer register means for storing addresses of locations in said memory for communication with said one I/O device via said bus,

sequence register means for storing an address of a location in said memory containing a channel program instruction which is to be executed next;

arithmetic logic unit (ALU) means comprising;

means for one of incrementing and decrementing addresses stored in said pointer register means,

means for computing the next address to be stored in said sequence register means,

means for computing an initial contents of each of said register means in said channel register means;

said memory containing a sequence of channel program instructions for each of said channels at locations in said memory whose addresses are sequentially stored in said sequence register means, said instructions comprising means for defining;

a set up operation wherein the contents of each of said registers in said channel register means is initialized in accordance with said initial contents computed by said ALU means,

an access operation wherein data is transferred on said bus between a location in said memory whose address is currently stored in said pointer register means and said one I/O device enabled by said resolver means.

9. The improvement of claim 8 wherein said channel register means further comprise:

channel status register means for storing a data count corresponding to a data block size to be transferred in the corresponding channel, and

counter register means for storing a repeat count of the number of times an access operation is to be repeated in a corresponding channel to complete a corresponding channel program, wherein the contents of said channel status register means and said counter register means is initialized in accordance with said sequence of program instructions corresponding to said set up operation.

10. The improvement of claim 9 further comprising means for causing said DMA controller to relinquish access to said bus whenever one of:

the amount of data transferred on said bus during said access operation equals the data count stored in said channel status register, and

the access instruction has been executed repeatedly a number of times equal to said repeat count stored in said count register means.

11. The improvement of claim 8 wherein a central processing unit (CPU) is connected to said bus, said DMA controller further comprising:

means for asserting a bus hold request to said CPU whenever said resolver means selects one of said I/O devices for access to said bus, and

wherein said CPU comprises means for enabling said DMA controller to have access or permit the selected one I/O device to have access to said bus by transmitting a bus hold acknowledgment to said DMA controller.

12. The improvement of claim 11 further comprising:

burst register means for storing a minimum amount of time that said DMA controller maintains access to said bus upon being enabled by said CPU to have access to said bus; and

means for ignoring control signals from said CPU removing access to said bus from said DMA controller.

13. The improvement of claim 8 wherein one of said I/O devices comprises another DMA controller which is a slave to said DMA controller.

14. The improvement of claim 8 wherein said global register means further comprise:

bandwidth register means for defining for each I/O device the amount of time that it is permitted to have access to said bus relative to the amount of time that it does not have access to said bus, and

means for terminating the access of said one I/O device upon expiration of said amount of time,

wherein the contents of said bandwidth register is initialized in accordance with said sequence of instructions corresponding to said set up operation.