Programmable DMA controller
First Claim
1. In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of said I/O devices to said memory, a direct memory access (DMA) controller for regulating access of each of said I/O devices to said bus, said DMA controller comprising:
- global register means comprising;
priority register means for storing priority parameters for each of said I/O devices, said parameters corresponding to relative priorities accorded to simultaneously pending requests by at least some of said plural I/O devices for access to said bus,interrupt register means for storing requests for access to said bus from respective ones of said I/O devices,resolver means for determining from said priority register means and said interrupt register means one of said I/O devices to have access to said bus and for transmitting an acknowledgment to said one I/O device enabling said device to communicate with said memory on said bus;
channel register means comprising;
pointer register means for storing addresses of locations in said memory for communication with said one I/O device via said bus,sequence register means for storing an address of a location in said memory containing a channel program instruction which is to be executed next;
arithmetic logic unit (ALU) means comprising;
means for one of incrementing and decrementing addresses stored in said pointer register means in accordance with a corresponding channel program instruction,means for computing the next address to be stored in said sequence register means in accordance with a corresponding channel program instruction,means for computing an initial contents of each of said register means in said channel register means in accordance with a corresponding channel program instruction;
said memory containing a sequence of channel program instructions for each of said channels at locations in said memory whose addresses are sequentially stored in said sequence register means, said instructions comprising means for defining;
a set up operation wherein the contents of each of said registers in said channel register means is initialized in accordance with said initial contents computed by said ALU means,an access operation wherein data is transferred on said bus between a location in said memory whose address is currently stored in said pointer register means and said one I/O device enabled by said resolver means.
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Accused Products
Abstract
In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.
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Citations
14 Claims
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1. In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of said I/O devices to said memory, a direct memory access (DMA) controller for regulating access of each of said I/O devices to said bus, said DMA controller comprising:
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global register means comprising; priority register means for storing priority parameters for each of said I/O devices, said parameters corresponding to relative priorities accorded to simultaneously pending requests by at least some of said plural I/O devices for access to said bus, interrupt register means for storing requests for access to said bus from respective ones of said I/O devices, resolver means for determining from said priority register means and said interrupt register means one of said I/O devices to have access to said bus and for transmitting an acknowledgment to said one I/O device enabling said device to communicate with said memory on said bus; channel register means comprising; pointer register means for storing addresses of locations in said memory for communication with said one I/O device via said bus, sequence register means for storing an address of a location in said memory containing a channel program instruction which is to be executed next; arithmetic logic unit (ALU) means comprising; means for one of incrementing and decrementing addresses stored in said pointer register means in accordance with a corresponding channel program instruction, means for computing the next address to be stored in said sequence register means in accordance with a corresponding channel program instruction, means for computing an initial contents of each of said register means in said channel register means in accordance with a corresponding channel program instruction; said memory containing a sequence of channel program instructions for each of said channels at locations in said memory whose addresses are sequentially stored in said sequence register means, said instructions comprising means for defining; a set up operation wherein the contents of each of said registers in said channel register means is initialized in accordance with said initial contents computed by said ALU means, an access operation wherein data is transferred on said bus between a location in said memory whose address is currently stored in said pointer register means and said one I/O device enabled by said resolver means. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In a direct memory access controller for a data system having a memory, plural input/output (I/O) devices and a bus connecting each of said I/O devices to said memory, the direct memory access (DMA) controller for regulating access of each of said I/O devices to said bus, the improvement comprising:
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global register means comprising; priority register means for storing priority parameters for each of said I/O devices, said parameters corresponding to relative priorities accorded to simultaneously pending requests by at least some of said plural I/O devices for access to said bus, interrupt register means for storing requests for access to said bus from respective ones of said I/O devices, resolver means for determining from said priority register means and said interrupt register means one of said I/O devices to have access to said bus and for transmitting an acknowledgment to said one I/O device enabling said device to communicate data on said bus; channel register means comprising; pointer register means for storing addresses of locations in said memory for communication with said one I/O device via said bus, sequence register means for storing an address of a location in said memory containing a channel program instruction which is to be executed next; arithmetic logic unit (ALU) means comprising; means for one of incrementing and decrementing addresses stored in said pointer register means, means for computing the next address to be stored in said sequence register means, means for computing an initial contents of each of said register means in said channel register means; said memory containing a sequence of channel program instructions for each of said channels at locations in said memory whose addresses are sequentially stored in said sequence register means, said instructions comprising means for defining; a set up operation wherein the contents of each of said registers in said channel register means is initialized in accordance with said initial contents computed by said ALU means, an access operation wherein data is transferred on said bus between a location in said memory whose address is currently stored in said pointer register means and said one I/O device enabled by said resolver means. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification