CMOS to ECL translator with incorporated latch
First Claim
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1. A latch circuit comprising:
- a first MOS transistor having a first terminal coupled to a first output node, a gate terminal coupled to a first latch input for performing a set function on said latch circuit, and a second terminal coupled to a first node;
a second MOS transistor having a first terminal coupled to a second output node, a gate terminal coupled to a second latch input for performing a reset function on said latch circuit, and a second terminal coupled to said first node;
a third MOS transistor having a first terminal coupled to said first output node, a second terminal coupled to said first node and a gate coupled to said second output node;
a fourth MOS transistor having a first terminal coupled to said second output node, a second terminal coupled to said first node and a gate coupled to said first output node;
a first resistor having a first terminal coupled to said first output node and a second terminal coupled to a first voltage;
a second resistor having a first terminal coupled to said second output terminal and a second terminal coupled to said first voltage;
a constant current source coupled between said first node and a second voltage; and
where said first and second latch inputs operate in a first voltage range and where said first and second output nodes operate in a second voltage range.
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Abstract
An electrical circuit is disclosed which implements a CMOS to ECL translator with an incorporated latch. The invention provides a circuit which uses a small number of devices, and provides fast transition times with low power consumption.
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Citations
7 Claims
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1. A latch circuit comprising:
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a first MOS transistor having a first terminal coupled to a first output node, a gate terminal coupled to a first latch input for performing a set function on said latch circuit, and a second terminal coupled to a first node; a second MOS transistor having a first terminal coupled to a second output node, a gate terminal coupled to a second latch input for performing a reset function on said latch circuit, and a second terminal coupled to said first node; a third MOS transistor having a first terminal coupled to said first output node, a second terminal coupled to said first node and a gate coupled to said second output node; a fourth MOS transistor having a first terminal coupled to said second output node, a second terminal coupled to said first node and a gate coupled to said first output node; a first resistor having a first terminal coupled to said first output node and a second terminal coupled to a first voltage; a second resistor having a first terminal coupled to said second output terminal and a second terminal coupled to said first voltage; a constant current source coupled between said first node and a second voltage; and where said first and second latch inputs operate in a first voltage range and where said first and second output nodes operate in a second voltage range. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification