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CMOS to ECL translator with incorporated latch

  • US 5,214,317 A
  • Filed: 05/04/1992
  • Issued: 05/25/1993
  • Est. Priority Date: 05/04/1992
  • Status: Expired due to Term
First Claim
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1. A latch circuit comprising:

  • a first MOS transistor having a first terminal coupled to a first output node, a gate terminal coupled to a first latch input for performing a set function on said latch circuit, and a second terminal coupled to a first node;

    a second MOS transistor having a first terminal coupled to a second output node, a gate terminal coupled to a second latch input for performing a reset function on said latch circuit, and a second terminal coupled to said first node;

    a third MOS transistor having a first terminal coupled to said first output node, a second terminal coupled to said first node and a gate coupled to said second output node;

    a fourth MOS transistor having a first terminal coupled to said second output node, a second terminal coupled to said first node and a gate coupled to said first output node;

    a first resistor having a first terminal coupled to said first output node and a second terminal coupled to a first voltage;

    a second resistor having a first terminal coupled to said second output terminal and a second terminal coupled to said first voltage;

    a constant current source coupled between said first node and a second voltage; and

    where said first and second latch inputs operate in a first voltage range and where said first and second output nodes operate in a second voltage range.

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