Method and apparatus for partial response demodulation

• US 5,214,390 A
• Filed: 03/16/1992
• Issued: 05/25/1993
• Est. Priority Date: 03/16/1992
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Montreuil, Leo
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/851,445
• Time in Patent Office: 435 Days
• Field of Search: 329/304, 329/306, 329/307, 329/308, 329/309, 329/310, 375/39, 375/52, 375/80, 375/82, 375/83
• US Class Current: 329/309
• CPC Class Codes: H04L 2027/0051 Harmonic tracking
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 5/06 the signals being represented by different frequencies combined with time-division multiplexing H04L5/26

Abstract

A digital audio communication system includes a digital modulation and demodulation scheme which efficiently uses the bandwidth and channel spacing of a cable television system. A 30 channel digital bit stream is demultiplexed into six groups of five channels. Each group of channels thereafter modulates a carrier by a quadrature partial response (QPR) process. The QPR signal, an amplitude modulated, double sideband, carrier suppressed (AM DSBSC) signal, is then transmitted over the cable system to a multiplicity of subscribers, each of which has a QPR demodulator. The demodulators are of the decision feedback type having a modified Costas loop carrier recovery circuit. The grouping of an odd number (five) of digital audio channels per QPR modulator minimizes error propagation due to the correlative QPR demodulation process. The decision feedback decoding is implemented in simple current nodes where a bilevel output from the decoded data is subtracted from a tertiary level output of a mixer. The resulting bilevel current is converted to a voltage, filtered, and limited to produce a logic output level. The modified Costas loop provides an error voltage based upon the difference of the received data states versus the nominal data states and the quadrant the data occupies. The error voltage is generated by differencing the outputs of two analog switches which have as their inputs analog signals representative of the amplitude level of the data and its inverse of one phase. The sign of the data bit of the opposite phase is used to control the switch and thus select which signal is used.

Claims

1. A demodulator for a quadrature partial response (QPR) signal of the form M_i (t) * sin(ω

_c t)+M_q (t) * cos(ω

_c t), where M_i (t) and M_q (t) are encoded partial response information modulations of the inphase and quadrature phases of a carrier of frequency (ω

_c t), said demodulator comprising;

means for decoding a data clock from the QPR signal and for generating a recovered data clock signal;

means for generating a demodulating carrier of frequency (ω

_c t) with inphase and quadrature phases coherent with the QPR signal carrier;

first means for mixing the QPR signal with the inphase phase of said demodulating carrier, said first mixing means generating a current as a function of time including the component M_i (t);

means for determining whether M_i (t) is positive or negative at a sampling time determined by said recovered data clock signal;

means for generating a digital output depending upon the sign determination of M_i (t) where said digital output is one state if M_i (t) is positive and the other state if negative;

means for subtracting an amount of current equivalent to the previous state of said digital output generating means from the output of said first mixing means;

second means for mixing the QPR signal with the quadrature phase of said demodulating carrier, said second mixing means generating a current as a function of time including the component M_q (t);

means for determining whether M_q (t) is positive or negative at a sampling time determined by said recovered data clock signal;

means for generating a digital output depending upon the sign determination of M_q (t) where said digital output is one state if M_q (t) is positive and the other state if negative; and

means for subtracting an amount of current equivalent to the previous state of said digital output generating means from the output of said second mixing means.

2. A QPR demodulator as set forth in claim 1 wherein said first mixing means generates a current including a first component signal including M_i (t) and cos(2ω

_c t) and wherein said second mixing means generates a current including a second component signal including M_q (t) and cos(2ω

_c t) which further includes;

means for filtering M_i (t) from said first component signal; and

means for filtering M_q (t) from said second component signal.

3. A QPR demodulator as set forth in claim 2 wherein:

said means for filtering said first component signal includes a current to voltage converter; and

said means for filtering said second component signal includes a current to voltage converter.

4. A QPR demodulator as set forth in claim 3 wherein:

said first digital output generating means includes an analog to digital converter for converting the analog voltage level of M_i (t) to a first digital signal having two logic states; and

said second digital output generating means includes an analog to digital converter for converting the analog voltage level of M_q (t) to a second digital signal having two logic states.

5. A QPR demodulator as set forth in claim 4 wherein:

said first subtracting means further includes means for converting said first digital signal to an analog current signal having two current levels corresponding to the states of the digital signal; and

said second subtracting means further includes means for converting said second digital signal to an analog current signal having two current levels corresponding to the states of the digital signal.

6. A QPR demodulator as set forth in claim 5 wherein said first subtracting means further comprises:

a current source adapted to supplying a current level +i to a current combination node;

a current source adapted to subtract a current level -2i from said combination node; and

means for switching, coupled between said combination node and said current sink, having a control terminal coupled to said first digital signal, said switching means coupling said current sink to said combination node for one state of the first digital signal and decoupling said current sink from said combination node for the other state of the first digital signal, whereby a current level of +i is supplied to said combination node for one state of said first digital signal and a current level of -i is subtracted from said combination node for the other state of said first digital signal.

7. A QPR demodulator as set forth in claim 5 wherein said second subtracting means further comprises:

a current source adapted to supply a current +i to a combination node;

a current source adapted to subtract a current level -2i from said the combination node; and

means for switching, coupled between said combination node and said current sink, having a control terminal coupled to said second digital signal, said switching means coupling said current sink to said combination node for one state of the second digital signal and decoupling said current sink from said combination node for the other state of the second digital signal, whereby a current level of +i is supplied to said combination node for one state of said second digital signal and a current level of -i is subtracted from said combination node for the other state of said second digital signal.

8. A QPR demodulator as set forth in claim 3 wherein said current to voltage converter comprises;

an impedance coupled between a voltage source and said current combination node; and

a voltage to voltage converter having a relatively high input impedance which is coupled to said node.

9. A QPR demodulator as set forth in claim 8 wherein said voltage to voltage converter includes:

an NPN transistor configured as an emitter follower having its base coupled to the combination node and its emitter coupled to ground through an emitter impedance, wherein said voltage signal is output from the junction between the emitter terminal of said transistor and said emitter impedance.