ATM switching system and adaptation processing apparatus

• US 5,214,642 A
• Filed: 01/23/1991
• Issued: 05/25/1993
• Est. Priority Date: 02/21/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd., Nippon Telegraph and Telephone Corporation
• Original Assignee: Hitachi, Ltd., Nippon Telegraph and Telephone Corporation
• Inventors: Ichikawa, Hiroyuki, Gohara, Shinobu, Kunimoto, Masao, Iwaki, Shinichi, Kawakita, Kenji, Kashio, Jiro
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HSU, ALPUS
• Application Number:
  US07/645,041
• Time in Patent Office: 853 Days
• Field of Search: 370/58.1, 370/58.2, 370/58.3, 370/60, 370/60.1, 370/61, 370/79, 370/82, 370/83, 370/94.1, 370/99
• US Class Current: 370/471
• CPC Class Codes: G06F 2205/066 User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: H04J 3/247 ATM or packet multiplexing
• CPC Class Codes: H04L 2012/563 Signalling, e.g. protocols, reference model
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/555 Error detection
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An adaptation processing apparatus for assembling received data units of a fixed length to provide variable length data units and transmitting the variable length data units to a plurality of variable length data unit processors while assembling variable length data units received from said plurality of the variable length data unit processors to provide fixed length data units for transmission thereof. An ATM switching system includes the adaptation processing apparatus, a signal processing unit including the plurality of variable length data unit processors mentioned above, and first-in first-out mechanisms for the variable length data units provided in the adaptation processing apparatus in association with every one of the plural variable length data unit processors.

Claims

1. An adaptation processing apparatus for assembling received data units of a fixed length to form data units of a variable length and transmitting the variable length data units to a plurality of high-rank devices respectively for processing the variable length data units, comprising:

a memory which is partitioned into a plurality of buffers, each buffer having a capacity for storing a fixed length data unit, to provide first, second and third first-in-first-out (FIFO) storages;

the first storages, provided for every identifier of the fixed length data units, each first FIFO storage including means for storing fixed length data units of corresponding identifiers transmitted through a line, a plurality of fixed length data units stored in a first FIFO storage comprise a variable length data unit;

the second FIFO storages, provided for every high-rank device, each second FIFO storage including means for storing the variable length data unit stored in said first FIFO storage and sending the stored variable length data unit to a corresponding one of the high-rank devices; and

the third FIFO storage for storing an empty buffer, wherein when data stored in one of said second FIFO storages is read, the buffer of the one of said second FIFO storages is stored in said third FIFO storage as the empty buffer.

2. The adaptation processing apparatus according to claim 1, further comprising:

a fourth FIFO storage obtained by partitioning the memory into the plurality of the buffers each having the capacity of the fixed length data unit, wherein

when data stored in one of said first FIFO storages includes error data, said fourth FIFO storage stores all data stored in the one of said first FIFO storages, and wherein

when the data stored in said fourth FIFO storage is read, the buffer of said fourth FIFO storage is stored in said third FIFO storage as the empty buffer.

3. The adaptation processing apparatus according to claim 1, wherein said buffers are linked by pointers to form said first to third FIFO storages and data transfer among said first to third FIFO storages is performed by controlling said pointers.

5. The adaptation processing apparatus according to claim 1, further comprising:

means for measuring a number of fixed length data units stored in each of said first FIFO storages and scrapping the fixed length data units stored in said first FIFO storage when the measured number exceeds a predetermined value.

6. The adaptation processing apparatus according to claim 1, further comprising:

means for arbitrarily setting a time period between the variable length data units sequentially sent from each of said second FIFO storages to the corresponding high-rank device.

7. An adaptation processing apparatus for assembling received data units of a fixed length to form data units of a variable length and transmitting the variable length data units to a plurality of high-rank devices respectively for processing the variable length data units, comprising:

a memory which is partitioned into a plurality of buffers, each buffer having a capacity for storing a fixed length data unit to provide first, second and third storage units;

the first storage units, provided for every identifier of the fixed length data units, each first storage unit including means for storing fixed length data units of corresponding identifiers transmitted through a line, a plurality of fixed length data units stored in a first storage unit comprise a variable length data unit;

the second storage units, provided for every high-rank device, each second storage unit including means for storing the variable length data unit stored in said first storage unit and sending the stored variable length data unit to a corresponding one of the high-rank devices; and

the third storage unit for storing an empty buffer, wherein when data stored in one of said second storage units is read, the buffer of the one of said second storage units is stored in said third storage unit as the empty buffer.

8. The adaptation processing apparatus according to claim 7, further comprising:

a fourth storage unit obtained by partitioning the memory into the plurality of the buffers each having the capacity of the fixed length data unit, wherein

when data stored in one of said first storage units includes error data, said fourth storage unit stores all data stored in the one of said first storage units, and wherein

when the data stored in said fourth storage unit is read, the buffer of said fourth storage unit is stored in said third storage unit as the empty buffer.

9. An adaptation processing apparatus for assembling received data units of a fixed length to form data units of a variable length and transmitting the variable length data units to a plurality of high-rank devices respectively for processing the variable length data units, comprising:

a memory which is partitioned into a plurality of buffers, each buffer having a capacity for storing a fixed length data unit to provide first, second and third first-in-first-out (FIFO) storages;

the first FIFO storages, provided for every identifier of the fixed length data units, each first FIFO storage including means for storing the fixed length data units of corresponding identifiers, a plurality of fixed length data units stored in a first FIFO storage comprise a variable length data unit;

means for receiving the fixed length data unit transmitted through a line and storing the received fixed length data unit into the first FIFO storage of a corresponding identifier, the first FIFO storage storing the variable length data unit;

the second FIFO storage being provided for every high-rank device;

means for transferring the variable length data unit stored in said first FIFO storage to said second FIFO storage;

means for sending the variable length data unit transferred to said second FIFO storage to a corresponding one of the high-rank device; and

the third FIFO storage for storing an empty buffer, wherein when data stored in one of said second FIFO storages is read, the buffer of the one of said second FIFO storages is stored in said third FIFO storage as the empty buffer.

4. The adaptation processing apparatus according to claim 10, further comprising:

means for measuring a resident time of the fixed length data units stored in each of said first FIFO storages and scrapping the fixed length data unit stored for a time exceeding a predetermined duration.

10. The adaptation processing apparatus according to claim 9, further comprising:

a fourth FIFO storage obtained by partitioning the memory into the plurality of the buffers, each buffers having the capacity of the fixed length data unit;

means for, when data stored in one of said first FIFO storages includes error data, storing all data stored in the one of said first FIFO storages into said fourth FIFO storage, wherein

when the data stored in said fourth FIFO storage is read, the buffer of said fourth FIFO storage is stored in said third FIFO storage as the empty buffer.

11. The adaptation processing apparatus according to claim 9, wherein said means for transferring includes means for transferring a table defining relations between the identifiers and the high-rank devices, and means for transferring the variable length data unit stored in said first FIFO storage to said second FIFO storage with reference to said table.

12. An adaptation processing apparatus for assembling received data units of a fixed length to form data units of a variable length and transmitting the variable length data units to a plurality of high-rank devices respectively for processing the variable length data units, comprising:

a memory which is partitioned into a plurality of buffers, each buffer having a capacity for storing a fixed length data unit to provide first, second and third first-in-first-out (FIFO) storages;

the first FIFO storages, provided for every identifier of the fixed length data units, each first FIFO storage including means for storing the fixed length data units of corresponding identifiers, a plurality of fixed length data units stored in a first FIFO storage comprise a variable length data unit;

means for receiving each fixed length data unit transmitted through a line and storing the received fixed length data unit into the first FIFO storage in accordance with a corresponding identifier;

the second FIFO storages being provided for every high-rank device;

means for transferring the buffer of one of said first FIFO storages to said second FIFO storage when the variable length data unit is stored in the one of said first FIFO storages;

means for sending the variable length data unit of the buffer transferred to said second FIFO storage to a corresponding one of the high-rank device; and

the third FIFO storage for storing an empty buffer, wherein when data stored in one of said second FIFO storages is read, the buffer of the one of said second FIFO storages is stored in said third FIFO storage as the empty buffer, and wherein the empty buffer of said third FIFO storage is transferred to said second FIFO storage when said means for receiving receives a fixed length data unit.

13. The adaptation processing apparatus according to claim 12, further comprising:

a fourth FIFO storage obtained by partitioning the memory into the plurality of the buffers each having the capacity of the fixed length data unit;

means for, when data stored in one of said first FIFO storages includes error data, storing all data stored in the one of said first FIFO storages into said fourth FIFO storage, wherein

when the data stored in said fourth FIFO storage is read, the buffer of said fourth FIFO storage is stored in said third FIFO storage as the empty buffer.

14. The adaptation processing apparatus according to claim 12, wherein said buffers are linked by pointers to form said first to third FIFO storages and buffer transfer among said first to third FIFO storages is performed by controlling said pointers.

15. A broadband communication system comprising:

interface means for communicating a data unit of a fixed length through a transmission line;

an asynchronous transfer mode switching means operatively connected to said interface means for communicating the fixed length data unit therewith; and

an adaptation processing apparatus for receiving the fixed length data unit from said asynchronous transfer mode switching means, said adaptation processing apparatus comprising

a memory which is partitioned into a plurality of buffers, each buffer having a capacity for storing a fixed length data unit, to provide first, second and third first-in-first-out (FIFO) storages;

the first FIFO storages, provided for every identifier of the fixed length data units, each first FIFO storage including means for storing fixed length data units of corresponding identifiers transmitted through a line, a plurality of fixed length data units stored in a first FIFO storage comprise a variable length data unit;

the second FIFO storages, provided for every high-rank device, each second FIFO storage including means for storing the variable length data unit stored in said FIFO storage and sending the stored variable length data unit to a corresponding one of the high-rank devices; and

,

the third FIFO storage for storing an empty buffer, wherein when data stored in one of said second FIFO storages is read, the buffer of the one of said second FIFO storages is stored in said third FIFO storage as the empty buffer.

16. The broadband communication system according to claim 15, further comprising:

a fourth FIFO storage obtained by partitioning the memory into the plurality of the buffers each having the capacity of the fixed length data unit, wherein

when data stored in one of said first FIFO storages includes error data, said fourth FIFO storage stores all data stored in the one of said first FIFO storages, and wherein

when the data stored in said fourth FIFO storage is read, the buffer of said fourth FIFO storage is stored in said third FIFO storage as the empty buffer.

17. The broadband communication system according to claim 15, wherein said buffers are linked by pointers to form said first to third FIFO storages and data transfer among said first to third FIFO storages is performed by controlling said pointers.

18. The broadband communication system according to claim 15, further comprising:

means for measuring a resident time of the fixed length data units stored in each of said first FIFO storages and scrapping the fixed length data unit stored for a time exceeding a predetermined duration.

19. The broadband communication system according to claim 15, further comprising:

means for measuring a number of fixed length data units stored in each of said first FIFO storages and scrapping the fixed length data units stored in said first FIFO storage when the measured number exceeds a predetermined value.

20. The broadband communication system according to claim 15, further comprising:

means for arbitrarily setting a time period between the variable length data units sequentially sent from each of said second FIFO storages to the corresponding high-rank device.

21. The broadband communication system according to claim 15, further comprising:

means for detecting whether or not the fixed length data unit received from said asynchronous transfer mode switching means includes a control cell for use in said broadband communication system; and

means for, when the control cell is detected in the received fixed length data unit, sending the detected control cell to means for processing the control cell.

22. The broadband communication system according to claim 21, wherein the control cell includes information such as setting and disuse of a root.