Alternate processor continuation of task of failed processor

• US 5,214,652 A
• Filed: 03/26/1991
• Issued: 05/25/1993
• Est. Priority Date: 03/26/1991
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sutton, Arthur J.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/675,393
• Time in Patent Office: 791 Days
• Field of Search: 371/9.1, 371/12, 371/13, 371/11.3
• US Class Current: 714/10
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space

Abstract

Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored in predetermined storage locations by the the failing processor or by a service processor (SP) when the failing processor has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture. When a failed processor is detected, the SP issues an external interruption to other processors in the system that are operable for continuing the execution of the failed processor task after the required information is stored. Special indicators are stored in predetermined places in the system and/or microcode memory that is accessible to the SP and to the healthy processors in the system selectable for continuing the task'"'"' s execution.

Claims

1. A method in a multi-processor computer system of continuing the execution of a program or program task which is terminated before completion when is executing on a processor which fails due to a hard error condition, comprising the steps of:

copying contents of registers in a failing processor into storage to store a predetermined program continuation interruption state when the processor detects a hard error condition;

sending a signal identifying the failing processor to an other processor which is operational;

checking by the other processor of validity of contents stored by the copying step; and

signalling healthy processor(s) in the system of a request for a healthy processor to continue execution of the program or program task if the checking step finds validity;

selecting of a healthy processor to continue execution of the program or program task by signalling remaining healthy processor(s) of a selection, and

loading into a selected processor from storage the stored program continuation interruption state of the failing processor to continue execution of the program or program task from a last successfully executed instruction without having any abnormal end indicated for the program or program task.

2. A method of continuing the execution of a program as defined in claim 1, further comprising:

setting an indicator field in storage for identifying the failing processor to an operating system and for indicating the failing processor is terminating operation for the program or program task.

3. A method of continuing the execution of a program as defined in claim 1, further comprising:

signalling by the failing processor to a service processor of the processor failure; and

the copying of the contents of the registers in the failing processor being done by the failing processor if the failing processor is able, but the copying being done by the service processor if the failing processor is not able.

4. A method of continuing the execution of a program as defined in claim 3, further comprising:

signalling by the service processor of a malfunction alert for the failing processor to at least one operational processor to request the operational processor to continue processing the terminated program.

5. A method of continuing the execution of a program as defined in claim 3, further comprising:

the storing of the register contents being done in a logout area in system main storage assigned for use by the failing processor.

6. A method of continuing the execution of a program as defined in claim 3, further comprising:

setting by the service processor of flag bits in a storage area accessible by a system control program controlling the operation of the failing processor and at least one other operational processor.

7. A method of continuing the execution of a program as defined in claim 3, further comprising:

stopping the operation of the failing processor to allow maintenance; and

setting by the service processor of a processor-stopped indicator field in a hardware storage area accessible by microcode/processor hardware operation but not by any operating system or application program, and stopping the failed processor operation.

8. A method of continuing the execution of a program as defined in claim 7, further comprising:

assuring that all outstanding stores done by the failing processor are at least on a bus to memory and external of the failing processor before stopping the operation of the failing processor.

9. A method of continuing the execution of a program as defined in claim 8, further comprising:

setting by the service processor in the storage area accessible by the system control program of validity indicator bits for conditions required for continuing execution of the terminated program.

10. A method of continuing the execution of a program as defined in claim 9, further comprising:

setting by the service processor in the storage area accessible by the system control program of validity indicator bits for the copied register contents.

11. A method of continuing the execution of a program as defined in claim 10, further comprising:

setting by the service processor in the storage area accessible by the system control program of a machine check old PSW (program status word) for indicating the address in the terminated program from the failed processor where the continuation of instruction processing is to occur.

12. A method of continuing the execution of a program as defined in claim 4, the signalling of a malfunction alert further comprising:

sending the malfunction alert signal to all operational processors to request at least one of the operational processors to continue processing the terminated program.

13. A method of continuing the execution of a program as defined in claim 12, the malfunction alert signal further comprising:

transmitting an external interruption signal to all operational processors.

14. A method of continuing the execution of a program as defined in claim 12, further comprising:

storing a malfunction alert signal with an identifier of the failed processor in a hardware storage area accessible by microcode/processor hardware operation but not by any operating system or application program assigned to each operational processor.

15. A method of continuing the execution of a program as defined in claim 13, further comprising:

stopping the operation of the failing processor when the microcode senses the MFA indication to allow maintenance on the failed processor; and

setting by the service processor of an identifier for the failed processor in the hardware storage area, and a selected operational processor sensing the identifier of the failed processor to determine its identification.

16. A method of continuing the execution of a program as defined in claim 12, further comprising:

testing the number of operational processors in the system to determine if there is at least one operational processor in the system; and

abnormally ending the terminated program if there is no operational processor in the system.

17. A method of continuing the execution of a program as defined in claim 12, further comprising:

selecting an operational processor as the continuing processor for continuing the execution of the program terminated on the failed processor as the first operational processor to become enabled for interruptions after the malfunction alert signalling.

18. A method of continuing the execution of a program as defined in claim 17, selecting operation further comprising:

interrupting an operational processor to select a processor to continue the execution of the terminated program.

19. A method of continuing the execution of a program as defined in claim 18, selecting operation further comprising:

selecting a processor different from the interrupted operational processor for continuing the execution of the terminated program.

20. A method of continuing the execution of a program as defined in claim 18, selecting operation further comprising:

selecting the interrupted operational processor as the processor for continuing the execution of the terminated program.

21. A method of continuing the execution of a program as defined in claim 20, further comprising:

preparing for the continued execution of the terminated program by initiating an operating system routine on the selected processor by fetching an address in a machine check new PSW in the saved information for the terminated program on the failed processor.

22. A method of continuing the execution of a program as defined in claim 21, further comprising:

executing the operating system routine on the selected processor to read a checkstop indicator field in the machine check interruption code stored in an area in main memory assigned to the failed processor in order for the selected processor to learn that the failed processor has failed, and continuing the execution of the terminated program only if the checkstop indicator field indicates a checkstopped condition.

23. A method of continuing the execution of a program as defined in claim 22, further comprising:

abnormally ending the terminated program if no checkstop condition is indicated in the checkstop indicator field in the machine check interruption code.

24. A method of continuing the execution of a program as defined in claim 22, the execution of the operating system routine further comprising:

testing the state of the validity bits in the machine check interruption code; and

abnormally ending the terminated program if any validity bit indicates an invalid state in the machine check interruption code.

25. A method of continuing the execution of a program as defined in claims 22 or 23, executing the operating system routine and further comprising the steps of:

accessing the register contents for which validity bits indicate a valid state;

using the valid register contents to identify resources allocated to the abnormally ended program; and

releasing the resources from the abnormally ended program by action of an operation system.

26. A method of continuing the execution of a program as defined in claim 1 by controlling the process of claim 1 with the steps of:

repeating the execution of an instruction a plurality of times as long as the instruction execution is detected to have an error, and detecting a solid error in the hardware of the processor when a predetermined number of repeated executions have occurred without the instruction executing error-free; and

then

initiating the process defined in claim 1.

27. A method of continuing the execution of a program as defined in claim 1 by controlling the process of claim 1 with the steps of:

detecting an error in the hardware of the processor when an instruction execution has occurred with an error condition; and

then

initiating the process defined in claim 1 even though the error condition of the processor hardware is an intermittent type of error condition.

28. A method of continuing the execution of a program as defined in claim 1 by controlling the process of claim 1 with the steps of:

detecting degradation in the state of the hardware of a processor caused by occasional removal of failing hardware components;

determining when the degradation state of the processor has exceeded a predetermined threshold level; and

initiating the process defined in claim 1 when the predetermined threshold level has been exceeded for continuing a current task on another processor before taking the processor off line for performing maintenance.

29. A method of continuing the execution of a program as defined in claim 28, in which the determining step comprises:

testing the performance rate of the processor in relation to a predetermined processor performance rate to find when the predetermined threshold level has been exceeded.