Code acquisition process and circuit for a spread-spectrum signal

• US 5,214,669 A
• Filed: 07/29/1991
• Issued: 05/25/1993
• Est. Priority Date: 10/12/1989
• Status: Expired due to Fees

• Current Assignee: Agence Spatiale Europeenne
• Original Assignee: Agence Spatiale Europeenne
• Inventors: Zarembowitch, Alain
• Primary Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US07/687,894
• Time in Patent Office: 666 Days
• Field of Search: 375/1
• US Class Current: 375/130
• CPC Class Codes: H04B 1/708 Parallel implementation

Abstract

The spread-spectrum signal (S1) is converted into a one-bit quantized binary signal (S2) and this signal is coupled to a plurality of parallel detection circuits (10), each of said detection circuits being adapted to detect a distinct code epoch. Each detection circuit (10) receives concurrently a shifted version of a binary reference code (CR) and produces a signal (B3) having a first binary state when the received signal corresponds to the code epoch of the detection circuit and having a second binary state should it be otherwise. The output signals (B3) are combined and/or encoded to identify the correct code epoch in order to demodulate the received signal. The invention is used in communication systems receivers.

Claims

1. A code acquisition circuit for a spread-spectrum signal receiver generated by modulation of an electrical signal with a binary code, comprising:

a zero-crossing detector for converting the spread-spectrum signal into a one-bit binary signal,

a plurality of binary detection circuits having their first inputs connected in parallel for receiving the one-bit binary signal, each detection circuit comprising;

an exclusive OR gate having an input for receiving the binary input signal and an input for receiving the binary reference code in a time shifted version and having an output for generating a despread binary signal,

first means for accumulating binary signals each time the signal has a logical state 1 during a predetermined first integration period to generate a first accumulated signal,

means for comparing the value of the first accumulated signal to two predetermined threshold levels and for generating a second binary signal having a logical state 1 when the first accumulated signal is between the two threshold levels,

second means for accumulating binary signals each time the second binary signal has a logical state 1 during a second predetermined integration period to generate a second accumulated signal, and

comparator means connected to the output of the second means for accumulating for generating a binary detection signal when the second accumulated signal exceeds a third predetermined threshold level;

a shift register advancing in response to clock pulses, the shift register having the output of each state thereof connected to a second input of a different detection circuit, the shift register having its input connected to receive a binary reference code whereby each state output of the register provides a time shifted version of the binary reference code, and

output means for combining and/or encoding the detection signals from all the detection circuits so as to identify the correct code epoch of the spread-spectrum signal.

2. An apparatus according to claim 1, wherein the means for comparing comprises comparators connected to the output of the first accumulating means to generate a first signal when the first accumulated signal exceeds a lower threshold level and to generate a second signal when the first accumulated signal exceeds an upper threshold level, and a logical circuit for combining the first and second signals and for generating the second binary signal in accordance with the logical function S4=B1·

OR·

B2.