Program execution apparatus for ensuring security of a program

• US 5,214,697 A
• Filed: 03/27/1991
• Issued: 05/25/1993
• Est. Priority Date: 03/27/1990
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Saito, Yasuo
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US07/676,118
• Time in Patent Office: 790 Days
• Field of Search: 380/4, 380/9, 380/23, 380/25, 380/28, 380/49, 380/50, 380/24, 235/379, 235/380
• US Class Current: 713/190
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A micro controller which has a first memory in which invertedly enciphered program data is stored, a second memory which stores cipher key data necessary for decoding the password stored in the first memory, a CPU which controls writing data to or reading data from the first and second memories and a unit which descrambles the cipher in the program data stored in the first memory based on the key data stored in the second memory, when the CPU accesses the first memory. The operation of this CPU is based on the program data which is decoded using the descrambling unit, which makes it possible to effectively block decoding or altering of programs and data.

Claims

1. A program execution apparatus comprising:

a first memory for storing enciphered program data of n bits;

a second memory for storing encoded key data which enables deciphering;

means for accessing said first and second memories;

memory access sense means for sensing accessing of said first and second memories;

decoding means for decoding said encoded key data stored in said second memory into decoded bits;

decipher means for deciphering said program data, said decipher means having n deciphering circuits provided for n data lines of said first memory means, said data lines corresponding to said n bits of said program data, said deciphering circuits being enabled when said decoded bits of said key data are enables; and

means for executing program data deciphered by said decipher means.

2. A program execution apparatus according to claim 1, wherein said second memory stores a plurality of different key data.

3. A program execution apparatus according to claim 1, wherein said deciphering circuit is comprised of holding means for holding bit status of said decoded bits of said key data, and a logical output means for outputting said bits of said program data in an inverted form when an output of said holding means is in a certain status.