Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism

• US 5,214,763 A
• Filed: 05/10/1990
• Issued: 05/25/1993
• Est. Priority Date: 05/10/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Vassiliadis, Stamatis, Blaner, Bartholomew
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): KIM, KENNETH S
• Application Number:
  US07/522,291
• Time in Patent Office: 1,111 Days
• Field of Search: 395/375, 395/800
• US Class Current: 712/212
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

Claims

1. In a digital computer system capable of processing two or more instructions in parallel, the combination comprising:

a larger-capacity, lower-speed storage mechanism for storing instructions to be processed;

a smaller-capacity, higher-speed cache storage mechanism for storing instructions with associated tag information;

an instruction fetch and issue unit;

and an instruction compounding mechanism coupled to receive an input of instructions from the lower-speed storage mechanism and to provide an output of instructions with associated tag information to the smaller-capacity storage mechanism and located between the lower-speed storage mechanism and the higher-speed storage mechanism, for analyzing these received instructions and producing the associated tag information for supplying these instructions and associated tag information to the higher-speed cache storage mechanism for storage therein prior to instruction fetch and issue by said instruction fetch and issue unit, the associated tag information comprising one or more bits indicating whether the instruction with which the tag is associated may be executed in parallel and which indicates which instructions may be processed in parallel with one another and having of a plurality of tag fields, a different one of which is associated with each instruction analyzed by the instruction compounding mechanism by an examination of the opcode; and

wherein the instruction compounding mechanism includes a plural-instruction instruction register for receiving a plurality of successive instructions from the lower-speed storage mechanism and means for producing a compoundability signal including a plurality of rule-based instruction analyzer mechanism, each of which analyzes the opcode of a different pair of side-by-side instructions in the instruction register, said means for producing a compoundability signal indicating whether or not the two instructions in its pair may be processed in parallel, and each instruction analyzer mechanism including logic circuitry for implementing rules which define which types of instructions are compatible for parallel execution in the particular instruction processing configuration used for the computer system, such logic circuitry providing said means for producing the compoundability signal for the analyzer mechanism,

and a tag generating mechanism responsive to the compoundability signals for generating the individual tag fields for the analyzed instructions in the instruction register for providing said tag fields as associated tags for the instructions analyzed and providing them as output to said higher-speed cache storage mechanism for storage and for access of the instructions by said instruction fetch and issue unit;

a plurality of functional instruction processing units of different functional types which operate in parallel with one another and wherein the tag information generated by the instruction compounding mechanism is used by said instruction fetch and issue unit in causing the issuance of two or more instructions in parallel from the higher-speed storage mechanism to appropriate functional units which can perform the required function for the issuing instructions.

2. The combination according to claim 1 wherein instruction compounding analysis is performed when an instruction cache miss occurs.

3. The combination according to claim 1 wherein as needed, the tagged instructions in the cache storage mechanism are fetched by the instruction fetch and issue unit, and as the tagged instructions are received by fetch and issue unit, their tag fields are examined to determine if they may be processed in parallel and their opcode fields are examined to determine which of the available functional units is most appropriate for their processing, and if the tag fields indicate that two or more of the instructions are suitable for processing in parallel, then they are sent to the appropriate ones of the functional units in accordance with the codings of their opcode fields and such instructions are then processed concurrently with one another by their respective functional units;

but when an instruction is encountered that is not suitable for parallel processing, then it is sent to the appropriate functional unit as determined by its opcode and it is thereupon processed alone and by itself by the selected functional unit.

4. The combination according to claim 1 wherein the instruction compounding unit for a case where a maximum of two instructions at a time may be processed in parallel in a particular computer configuration has, a one-bit tag field, and a tag bit value of "one" means that the instruction is a "first" instruction, a tag bit value of "zero" means that the instruction is "second" instruction, and may be executed in parallel with the proceeding first instruction, and an instruction having a tag bit value of one may be executed either by itself or at the same time and in parallel with the next instruction, depending on the tag bit value for such next instruction, each pairing of an instruction having a tag bit value of one with a succeeding instruction having a tag bit value of zero forming a compound instruction for parallel execution purposes, such that the instructions in such a pair may be processed in parallel with one another, and when the tag bits for two succeeding instructions each have a value of one, the first of these instructions is executed by itself in a nonparallel manner, and in a worst case, all of the instructions in the sequence would have a tag bit value of one and all of the instructions would be executed one at a time in a nonparallel manner.

5. The combination according to claim 1 wherein each instruction analyzer mechanism produces two of the compoundability signals, one of which indicates whether or not Instructions 0 and 1 may be processed in parallel, and another second compoundability signal indicates whether or not Instructions 1 and 2 may be processed in parallel;

and, in a similar way, a second compound analyzer mechanism produces a first compoundability signal which indicates whether or not Instructions 2 and 3 may be processed in parallel and a second compoundability signal which indicates whether Instructions 3 and 4 may be processed in parallel, and a third compound analyzer produces a first compoundability signal which indicates whether or not Instructions 4 and 5 may be processed in parallel and a second compoundability signal which indicates whether or not Instructions 5 and 6 may be processed in parallel, and a fourth compound analyzer mechanism produces a first compoundability signal which indicates whether or not Instructions 6 and 7 maybe processed in parallel and a second compoundability signal which indicates whether Instructions 7 and 8 may be processed in parallel.

6. The combination according to claim 1 wherein the tag generating mechanism is responsive to the compoundability signals appearing at the outputs of the analyzer units for generating the individual tag fields for the different instructions in the instruction register, and these tag fields are supplied to a tagged instruction register, as are the instructions themselves, the latter being obtained from an input instruction register, whereby the compounding unit output register, a tag field for each instruction, wherein each tag field is comprised of a single binary bit, and a tag bit value of "one" indicates that the immediately following instruction to which it is attached is a "first" instruction, and a tag bit value of "zero" indicates that the immediately following instruction is a "second" instruction, and an instruction having a tag bit value of one followed by an instruction having a tag bit value of zero indicates that those two instructions may be executed in parallel with one another, the tagged instructions in the compounding unit output register being supplied to the input of the compound instruction cache storage mechanism and stored into such cache storage mechanism.

7. The combination according to claim 1 wherein each compound analyzer mechanism includes instruction compatibility logic for examining the opcode of instruction pairs and determining whether these two opcodes are compatible for purposes of execution in parallel, and wherein the compabatiabilty logic includes logic circuitry for implementing rules which define which types of instructions are compatible for parallel execution in the particular hardware configuration used for the computer system being considered, and if the opcodes for the pair are compatible, then logic produces at its output a binary one level signal, and if they are not compatible, logic 30 produces a binary zero value on its output line, and wherein the compound analyzer further includes a second instruction compatibility logic for examining the opcodes of another pair of instructions and determining whether they are compatible for parallel execution by examination of their opcodes.

8. The combination according to claim 1 wherein the compound analyzer mechanism includes first register dependency logic for detecting conflicts in the usage of the general purpose registers designated by R1 and R2 fields of the instruction pair which are general purpose registered, such that the dependency logic may to detect the occurrence of a data depending condition wherein a second instruction (Instruction 2) needs to use the results obtained by the performance of the proceeding instruction (Instruction 0), in which case, either the second instruction can be executed by the dependency collapsing hardware, thus executing in parallel with the first instruction, or in the execution of the second instruction must await completion of the execution of the preceding instruction, and hence, cannot be executed in parallel with the preceding instruction, and wherein if there are no register dependencies which prevent execution of Instructions 0 and 1 in parallel, then the output line of dependency logic is given a binary value of one, and if there is a dependency, then it is given a binary value of zero.

9. The combination according to claim 8 wherein output lines from the instruction compatibility logic and the register dependency logic are connected to the two inputs of an AND circuit, wherein the output line of the AND circuit has a binary one value if the two opcodes being considered are compatible and if there are no register dependencies;

however, this binary one value on the AND circuit output line indicates that the two instructions being considered are compoundable, that is, are executable in parallel, but if, on the other hand, the AND circuit output line has a binary value of zero, then the two instructions are not compoundable and thus, there is produced on the AND circuit output line a first compoundability signal which indicates whether or not Instructions 0 and 1 may be processed in parallel, which signal is supplied to the tag generator.

10. The combination according to claim 1 wherein the logic compoundability internal circuitry for the instruction includes a first compatibility logic circuit which includes a plurality of decoders and AND circuits and an OR circuit, and a second instruction compoundability logic circuit which includes a plurality of decoders and AND circuits and an OR circuit with a middle decoder shared by both first and second logic circuitry.