Quantum well structures useful for semiconductor devices

• US 5,216,262 A
• Filed: 03/02/1992
• Issued: 06/01/1993
• Est. Priority Date: 03/02/1992
• Status: Expired due to Fees

• Current Assignee: TWK Technologies, Inc.
• Original Assignee: TWK Technologies, Inc.
• Inventors: Tsu, Raphael
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US07/844,725
• Time in Patent Office: 456 Days
• Field of Search: 257/21, 257/17, 257/22, 257/15, 257/20, 257/18, 257/24, 257/290, 257/411, 257/25, 257/23, 372/45
• US Class Current: 257/17
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane

Abstract

A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.

Claims

1. A quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated as a result of the release of stored strain energy.

2. A quantum well structure according to claim 1, wherein each of said layers has a thickness of 2 to 4 monolayers.

3. A quantum well structure according to claim 1, wherein the alternate layers are SiO₂ and Si in the barrier and the quantum well is Si.

4. A quantum well structure according to claim 2, wherein the alternate layers are SiO₂ and Si in the barrier and the quantum well is Si.

5. A quantum well structure according to claim 1, wherein the structure is doped to form desired junction characteristics.

6. A quantum well structure according to claim 1, wherein the layers are one of III-V and II-VI types.

7. A quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin monocrystalline quantum well sandwiched between said barrier regions, the quantum well consisting essentially of alternate strain layers forming a superlattice, each of said layers being so thin that no defects are generated as a result of the release of stored strain energy, each barrier region being thinner than said quantum well and consisting of an epitaxially grown monocrystalline semiconductor material.

8. A quantum well structure useful for semiconducting devices, said structure comprising two barrier regions and a thin epitaxially grown monocrystalline Si quantum well sandwiched between said barrier regions, each barrier region consisting essentially of alternate strain layers of SiO₂ and Si forming a superlattice, each of said layers being thinner than said quantum well and being so thin that no defects are generated as a result of the release of stored strain energy.

9. A quantum well structure according to claim 8, wherein each of said layers has a thickness of 2 to 4 monolayers.

10. A quantum well structure according to claim 8, wherein the structure is doped to form desired junction characteristics.

11. A metal oxide-semiconductor field effect transistor, comprising silicon having thereon a metal contact, the metal contact being separated from said silicon by an insulating layer, said insulating layer consisting essentially of alternate strain layers of SiO₂ and Si forming a superlattice, each of said layers being so thin that no defects are generated as a result of the release of stored strain energy.

12. A metal oxide-semiconductor field effect transistor according to claim 11, wherein each of said strain layers has a thickness of 2 to 4 monolayers.

13. A metal oxide-semiconductor field effect transistor according to claim 11, additionally having a layer of amorphous SiO₂ interposed between said metal contact and said insulating layer of alternate strain layers of SiO₂ and Si.

14. A metal oxide-semiconductor field effect transistor according to claim 13, wherein each of said strain layers has a thickness of 2 to 4 monolayers.

15. A metal oxide-semiconductor field effect transistor according to claim 13, wherein the thickness of the layer of amorphous SiO₂ is approximately the same as the thickness of said insulating layer of alternate strain layers of SiO₂ and Si.

16. A barrier material for use in semiconductor devices including quantum well structures, said material, consisting essentially of alternate strain layers of SiO₂ and Si forming a superlattice, each of said layers being so thin that no defects are generated as a result of release of stored strain energy.

17. A barrier material for use in semiconductor devices including quantum well structures according to claim 16, wherein each of said strain layers has a thickness of 2 to 4 monolayers.