Electrically-programmable semiconductor memories with buried injector region

• US 5,216,269 A
• Filed: 08/08/1991
• Issued: 06/01/1993
• Est. Priority Date: 03/31/1989
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Middelhoek, Jan, Wijburg, Rutger C. M., Hemink, Gerrit-Jan, Cuppens, Roger, Praamsma, Louis
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/745,992
• Time in Patent Office: 663 Days
• Field of Search: 357/23.5, 357/13, 357/13 PT, 365/185, 257/316, 257/318, 257/319, 257/320, 257/321
• US Class Current: 257/318
• CPC Class Codes: H01L 29/7884 charging by hot carrier injection

Abstract

Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern. A compact cell array layout can be formed with a common connection region for the injector regions of two adjacent cells and for either a source or drain region of four other adjacent cells. The control gate and an erase gate may both be coupled in the same manner to the charge-storage region, and the cell can be operated with complementary voltage levels for writing and erasing. A feed-back mechanism with the start of injection from the punch-through and injector regions can provide a well-defined charge level limit for the erasure.

Claims

1. An electrically-programmable semiconductor memory comprising a plurality of memory cells, each cell having a field-effect transistor with a charge-storage region whose charge state defines a memory state of the cell, the memory comprising a semiconductor body having for each cell a first insulating layer portion at a surface of the body over a first region of the body of a first conductivity type, the charge-storage region extending at a surface of the first insulating layer portion, programming means for each cell comprising an injector region of an opposite second conductivity type forming a p-n junction with the first region, and a control gate capacitively coupled to the charge-storgage region, characterized in that the injector region is located within the body below the first region below the charge-storage region, in that the control gate, the injector region and at least a drain of the transistor of each cell are provided with connection means for applying programming voltages to a cell to bias the control gate and the surface of the first region with respect to the injector region so as to set a desired charge-state of the charge-storage region of that cell by injection of hot charge-carriers through the first insulating layer portion vertically from the injector region, the first region having a sufficiently low doping concentration of the first conductivity type above the injector region to allow punch-through via a depletion layer vertically across the thickness of the first region to the injector region upon application of the programming voltages, in that hot charge carriers not injected into the first insulating layer portion are removed via the connection means to the drain of the transistor of that cell during the programming of that cell, and in that means are provided for restricting the lateral spread of the depletion layer at at least one side of the first region of each cell down to the injector region during punch-through vertically across the thickness of the first region, said means comprising at least one boundary region having a higher doping concentration of the first conductivity type than that of said first region, said boundary region being located at said at least one side of the first region of each cell.

2. A memory as claimed in claim 1, further characterized in that the boundary region is present above a peripheral part of the injector region to prevent parasitic connection of the injector region to the surface.

3. A memory as claimed in claim 2, further characterized in that each cell comprises in the body an island portion which includes the first region and which is bounded by an inset field insulating layer pattern at the surface of the body, and in that the boundary region adjoins the inset field pattern on at least one side of the island portion.

4. A memory as claimed in claim 3, further characterized in that the injector region extends below the first region between two opposite sides of the island portion, and in that the boundary region adjoins said two opposite sides.

5. A memory as claimed in claim 3, further characterized in that the connection means to the injector region comprises a buried layer of the second conductivity type which extends below an intermediate part of the field pattern, and in that the boundary region adjoins a side of this intermediate part.

6. A memory as claimed in claim 1, further characterized in that the transistor of each cell comprises source and drain regions present in an area of the body which is laterally separated from the first region by the boundary region.

7. A memory as claimed in claim 6 further characterized in that each cell comprises in the body an island portion across which the boundary region extends to separate the island portion laterally into opposite first and second ends, the first region and underlying injector region being present at the first end below one part of the charge-storage region, another part of the charge-storage region extending above at least a channel area between the transistor source and drain present at the second end.

8. A memory as claimed in claim 1 further characterized in that the transistor of each cell comprises source and drain regions of the second conductivity type which are each formed in a boundary region of the higher doping concentration of the first conductivity type, which boundary regions extend below the respective source and drain region and are separated from each other in a channel area of the transistor below the charge-storage region.

9. A memory as claimed in claim 1 further characterized in that the transistor of each cell comprises a drain region of a second conductivity type in the boundary region of high doping concentration of the first conductivity type, and the transistor also comprises a source region of the second conductivity type connected to the injector region.

10. A memory as claimed in claim 9, further characterized in that the charge-storage region extends over only a part of the length of the transistor channel between the source and drain regions, and in that an insulated gate extends over the remainder of the length of the transistor channel.

11. A memory as claimed in claim 10, further characterized in that said insulated gate is also capacitively coupled to the charge-storage region to provide an erase gate of the memory cell.

12. A memory as claimed in claim 1 further characterized in that each cell comprises an island portion of the body, and in that the island portions of two adjacent cells adjoin each other at a connection region of the second conductivity type which forms a common connection to the injector regions of the two adjacent cells.

13. A memory as claimed in claim 12, further characterized in that the connection region of the second conductivity type extends into four other adjacent island portions, in addition to said two adjacent island portions, to form a source and drain connection of the transistor in each of said four island portions.

14. A memory as claimed in claim 1 further characterized in that the control gate is present on a second insulating layer portion over the charge-storage region, and in that the charge-storage region is a floating gate between the first and second insulating layer portions.

15. A memory as claimed in claim 14, further characterized in that each memory cell comprises an erase gate which is present on the second insulating layer over the charge-storage region to permit electrical erasure of the memory state of that cell by applying an erasure voltage to the erase gate.

16. A memory as claimed in claim 1 further characterized by each memory cell comprising an erase gate coupled to the charge-storage means, and connection means for applying an erasure voltage to the erase gate to permit electrical erasure of the programmed charge-state of that cell while biasing the control gate at a lower voltage and while biasing the surface of the first region and the injector region at programming voltages to permit hot carrier injection into the charge-storage region from the injector region to compensate against over-erasure of the memory state.

17. A memory as claimed in claim 1 further characterized in that the injector region comprises an implanted n type well in a p type portion of the body, and in that a shallower implanted p type well is formed in a laterally adjacent part of the p type portion and overlaps and overdopes part of the area of the n type well to form the first region above the injector region.

18. An electrically-programmable semiconductor memory comprising a plurality of memory cells, each cell having a field-effect transistor with a charge-storage region whose charge state defines a memory state of the cell, the memory comprising a semiconductor body having for each cell a first insulating layer portion at a surface of the body over a first region of the body of a first conductivity type, the charge-storage region extending at a surface of the first insulating layer portion, programming means for each cell comprising an injector region of the opposite second conductivity type forming a p-n junction with the first region, and a control gate capacitively coupled to the charge-storage region, characterized in that the injector region is located within the body below the first region below the charge-storage region, in that the control gate, the injector region and at least a drain of the transistor of each cell are provided with connection means for applying programming voltages to a cell to bias the control gate and the surface of the first region with respect to the injector region so as to set a desired charge-state of the charge-storage region of that cell by injection of hot charge-carriers through the first insulating layer portion vertically from the injector region, the first region having a sufficiently low doping concentration of the first conductivity type above the injector region to allow punch-through via a depletion layer vertically across the thickness of the first region to the injector region upon application of the programming voltages, and in that hot charge carriers not injected into the first insulating layer portion are removed via the connection means to the drain of the transistor of that cell during the programming of that cell, further characterized by each memory cell comprising an erase gate coupled to the charge-storage means, and connection means for applying an erasure voltage to the erase gate to permit electrical erasure of the programmed charge-state of that cell while biasing the control gate at a lower voltage and while biasing the surface of the first region and the injector region at programming voltages to permit hot carrier injection into the charge-storage region from the injector region to compensate against over-erasure of the memory state.

19. A memory as claimed in claim 18, further characterized in that the injector region comprises an implanted n type well in a p type portion of the body, and in that a shallower implanted p type well is formed in a laterally adjacent part of the p type portion and overlaps and overdopes part of the area of the n type well to form the first region above the injector region.