Semiconductor device having a pad array carrier package

• US 5,216,278 A
• Filed: 03/02/1992
• Issued: 06/01/1993
• Est. Priority Date: 12/04/1990
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: McShane, Michael B., Lin, Paul T., Wilson, Howard P.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US07/841,765
• Time in Patent Office: 456 Days
• Field of Search: 357/68, 357/74, 357/70, 357/65, 357/71, 357/80, 174/52.4
• US Class Current: 257/688
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

Claims

1. A semiconductor device having a pad array carrier package comprising:

a carrier substrate having a die attach surface opposite a package mounting surface;

an electronic component mounted on the die attach surface;

a plurality of bonding pads arrayed on a face of the electronic component;

a plurality of vias in the carrier substrate, each via located at a predetermined distance from a selected bonding pad on the electronic component, wherein the predetermined distance is variable and is chosen to minimize signal impedance through the via;

a plurality of package leads overlying the die attach surface and extending from the die attach surface through the vias to terminal solder pads on the package mounting surface which are displaced away from the vias;

a plurality of solder balls which are displaced away from the vias and joined to the terminal solder pads;

electrical connections between the bonding pads on the electronic component and the package leads on the die attach surface; and

protection means overlying at least the electronic component and the electrical connections.

2. The semiconductor device of claim 1 wherein the plurality of package leads comprises:

a first plurality of metal lead traces overlying the die attach surface each having a bonding area adjacent to the electronic component and each extending through one of the plurality of vias; and

a second plurality of metal lead traces overlying the package mounting surface of the substrate each extending from one of the plurality of vias to one of the plurality of terminal solder pads.

15. The semiconductor device of claim 1 wherein the protection means comprises an epoxy compound set back from the edge of the carrier substrate.

16. The semiconductor device of claim 1 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate.

17. The semiconductor device of claim 1 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate and wrapping around the edge of the carrier substrate to overlie and edge portion of the package mounting surface.

18. The semiconductor device of claim 1 wherein the protection means comprises an epoxy compound overlying the die attach surface and extending to the edge of the carrier substrate.

3. A semiconductor device having a plastic pad array carrier package comprising:

an organic polymer substrate having a die attach surface and a package mounting surface;

an electronic component mounted on the die attach surface having a plurality of bonding pads on a face thereof;

a first plurality of lead traces on the die attach surface each having an inner bonding area adjacent to the electronic component;

electrical connections between the bonding pads on the electronic component and the inner bonding area of the first plurality of lead traces;

a second plurality of lead traces on the package mounting surface electrically coupled to the first plurality of lead traces by a plurality of vias in the substrate, each via located at a predetermined distance from the corresponding bonding pad such that the signal transmission through the first and second plurality of lead traces maximized;

a plurality of terminal solder pads on the package mounting surface which are displayed away from the vias;

a solder mask overlying the package mounting surface and a portion of the terminal solder pads; and

protection means overlying at least the electronic component and the electrical connections.

4. The semiconductor device of claim 3 further comprising a heat spreader attached to the face of the electronic component by a thermal coupling agent.

5. The semiconductor device of claim 3 further comprising:

a plurality of filled vias in the carrier substrate; and

a thermal plate attached to the filled vias.

6. The semiconductor device of claim 3 further comprising:

a plurality of filled vias in the carrier substrate; and

a plurality of thermal solder balls attached to the filled vias.

7. The semiconductor device of claim 6 further comprising a thermal plate attached to the thermal solder balls.

8. A semiconductor device having a plastic pad array carrier package comprising:

a carrier substrate having a die attach surface and package mounting surface, the package mounting surface including a component mounting area;

a plurality of irregularly spaced electrical vias in the carrier substrate extending from the die attach surface to the mounting surface;

means for attaching an external element extending from the die attach surface to the component mounting area on the package mounting surface;

an electronic component mounting on the die attach surface having a plurality of bonding pads of a face thereof;

a first plurality of lead traces on the die attach surface each having an inner bonding area adjacent to the electronic component and each extending to an individual electrical via;

electrical connections between the bonding pads on the electronic component and the inner bonding areas of the first plurality of lead traces;

a plating layer overlying a surface of the electrical vias;

a second plurality of lead traces on the package mounting surface electrically connected to the first plurality of lead traces by the plating layer and extending from the electrical vias to a plurality of regularly spaced terminal solder pads which are displaced away from the vias;

a plurality of solder balls which are displaced away from the vias and are bonded to the terminal solder pads;

a solder mask overlying the package mounting surface and a portion of the terminal solder pads; and

a molded plastic package body overlying at least the electronic component and the electrical connections.

9. The semiconductor device of claim 8 wherein the means for attaching an external element comprises a plurality of filled vias.

10. The semiconductor device of claim 9 the external element comprises a plurality of thermal solder balls bonded to the filled vias.

11. The semiconductor device of claim 9 wherein the external element comprises a thermal plate attached to the filled vias.

12. The semiconductor device of claim 10 wherein the external element comprises a electrical device selected from the group consisting of a decoupling capacitor and a resistor.

13. The semiconductor device of claim 8 further comprising an external power bus attached to the package mounting surface and electrically coupled to the electronic component.

14. The semiconductor device of claim 8 wherein the carrier substrate further comprises at least one additional insulating layer and at least one conductive layer electrically coupled to the electronic component.

19. A semiconductor device having a pad array carrier package comprising:

a carrier substrate having a die attach surface opposite a package mounting surface,

the package mounting surface partitioned in a periodic array with locations defined at selected positions in the array and terminal solder pads located at a plurality of the locations, and

the die attach surface partitioned in an a-periodic array with a plurality of via holes located at positions in the a-periodic array;

an electronic component mounted on the die attach surface and having a plurality of bonding pads arrayed on a face thereof;

a first plurality of lead traces overlying the die attach surface wherein each lead trace extends from a position proximate a selected bonding pad to a predetermined via; and

a second plurality of lead traces overlying the package mounting surface wherein each lead trace extends from one of the plurality of vias to a selected solder pad.

20. The semiconductor device of claim 19 further comprising protection means overlying at least the electronic component and the electrical connections.

21. The semiconductor device of claim 20 wherein the protection means comprises an epoxy compound set back from the edge of the carrier substrate.

22. The semiconductor device of claim 20 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate.

23. The semiconductor device of claim 20 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate and wrapping around the edge of the carrier substrate to overlie and edge portion of the package mounting surface.

24. The semiconductor device of claim 20 wherein the protection means comprises an epoxy compound overlying the die attach surface and extending to the edge of the carrier substrate.

25. A semiconductor device comprising:

an electronic component having a plurality of bonding pads on a face thereof;

a carrier substrate having a die attach surface opposite a package mounting surface, wherein the package mounting surface is partitioned in a periodic array with user defined locations at selected positions in the array and terminal solder pads located at a plurality of the locations;

a first plurality of lead traces overlying the die attach surface, each trace electrically connected to a selected bonding pad on the electronic component;

a second plurality of lead traces overlying the package mounting surface; and

a plurality of vias in the carrier substrate electrically coupling the first and second plurality of lead traces,

wherein each via is displaced away from a terminal solder pad, and

wherein each via is located at a predetermined position such that the signal inductance between the bonding pad and the terminal solder pad is minimized.

26. The semiconductor device of claim 25 further comprising protection means overlying at least the electronic component and the electrical connections.

27. The semiconductor device of claim 26 wherein the protection means comprises an epoxy compound set back from the edge of the carrier substrate.

28. The semiconductor device of claim 26 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate.

29. The semiconductor device of claim 26 wherein the protection means comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate and wrapping around the edge of the carrier substrate to overlie and edge portion of the package mounting surface.

30. The semiconductor device of claim 26 wherein the protection means comprises an epoxy compound overlying the die attach surface and extending to the edge of the carrier substrate.

31. A semiconductor device having a pad array carrier package for attachment to a package mounting substrate comprising:

a flexible carrier substrate having a die attach surface opposite a package mounting surface, the substrate having a coefficient of thermal expansion substantially the same as the package mounting substrate;

an electronic component mounted on the die attach surface;

a plurality of vias in the carrier substrate, each via located at a selected position on the die attach surface, wherein the distance between the electronic component and the selected position varies such that signal transmission to and from the electronic component is optimized;

a first plurality of lead traces overlying the die attach surface, wherein each lead trace is connected to a selected via and electrically coupled to the electronic component;

an array of terminal solder pads on the package mounting surface displaced away from the vias;

a second plurality of lead traces overlying the package mounting surface, wherein each trace connects one of the plurality of terminal solder pads to one of the first plurality of lead traces through the selected via;

compliant solder balls joined to the terminal solder pads and arranged so as to align with and contact selected bonding sites on the package mounting substrate;

a moulded package body overlying at least the electronic component and a portion of the first plurality of lead traces proximate the electronic component.

32. The semiconductor device of claim 31 wherein the moulded package body comprises an epoxy compound set back from the edge of the carrier substrate.

33. The semiconductor device of claim 31 wherein the moulded package body comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate.

34. The semiconductor device of claim 31 wherein the moulded package body comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate and wrapping around the edge of the carrier substrate to overlie and edge portion of the package mounting surface.

36. The semiconductor device of claim 31 wherein the moulded package body comprises an epoxy compound set back from the edge of the carrier substrate.

37. The semiconductor device of claim 31 wherein the moulded package body comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate.

38. The semiconductor device of claim 31 wherein the moulded package body comprises a plastic mold overlying the die attach surface and extending to the edge of the carrier substrate and wrapping around the edge of the carrier substrate to overlie and edge portion of the package mounting surface.

35. A semiconductor device having a flexible pad array carrier package for mounting on a mounting substrate comprising:

a single layer substrate having a die attach surface opposite a package mounting surface, the single layer substrate having a coefficient of thermal expansion substantially the same as the mounting substrate;

a plurality of vias extending through the carrier substrate from the die attach surface to the package mounting surface;

first lead traces overlying the die attach surface, wherein each lead trace is connected to a selected via;

an electronic component mounted on the die attach surface and electrically connected to the first plurality of lead traces;

an array of terminal solder pads on the package mounting surface and displaced away from the vias;

second lead traces on the package mounting surface connected to the vias and extending to the terminal solder pads; and

a moulded package body overlying at least the electronic component and a portion of the first lead traces proximate the electronic component.