Current mode logic circuits employing IGFETS

• US 5,216,295 A
• Filed: 08/30/1991
• Issued: 06/01/1993
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Hoang, Chinh L.
• Primary Examiner(s): Dzierzynski, Paul M.
• Assistant Examiner(s): RATLIFF, REGINALD A
• Application Number:
  US07/753,444
• Time in Patent Office: 641 Days
• Field of Search: 307/451, 307/448, 307/452, 307/453, 307/465
• US Class Current: 326/115
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

Counting and division circuits include an input differential stage connected to a cross-coupled differential stage. The input stage includes first and second IGFETS whose gate electrodes are respectively connected to first and second inputs, whose drains are respectively connected to first and second outputs, and whose sources are connected to the drain of a third IGFET whose source is grounded. The cross-coupled stage includes fourth and fifth IGFETs which are cross-coupled in that the gate of the fourth IGFET and the drain of the fifth IGFET are directly connected to the first output and the gate of the fifth IGFET and the drain of the fourth IGFET are directly connected to the second output. The sources of the fourth and fifth IGFETs are connected in common to the drain of a sixth IGFET whose source is grounded. Control signals are applied to the gates of the third and sixth IGFETS for selectively and alternately turning them on one at a time and, simultaneously, setting the level of the current flowing through the differentially connected IGFETS in their drain circuit.

Claims

1. The combination comprising:

first and second power terminals for the application therebetween of an operating potential;

first and second inputs for the application thereto of complementary input signals;

first and second outputs at which are produced complementary output signals in response to said input signals;

first, second, third, fourth, fifth and sixth insulated-gate-field-effect transistors (IGFETs) of one conductivity type;

each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode for controlling the conductivity of the path;

means connecting the drain of the first IGFET to said first output, the drain of the second IGFET to said second output, and the sources of said first and second IGFETS in common and via negligible impedance means to the drain of the third IGFET;

negligible impedance means connecting the drain of the fourth IGFET to said first output and the drain of the fifth IGFET to said second output and the sources of said fourth and fifth IGFETS in common to the drain of the sixth IGFET;

negligible impedance means connecting the control electrode of said fourth IGFET to the drain of said fifth IGFET at said second output and the control electrode of said fifth IGFET to the drain of said fourth IGFET at said first output;

negligible impedance means connecting the sources of said third and sixth IGFEs to said first power terminal;

means connecting the control electrodes of said first and second IGFETs to said first and second inputs, respectively;

means for applying control signals to the control electrodes of said third and sixth IGFETS for turning only one of them on at a time; and

means coupling said first and second outputs to said second power terminal.

2. The combination as claimed in claim 1, wherein the means connecting the conduction path of said first IGFET to said first output include the conduction path of a seventh IGFET;

and wherein the means connecting the conduction path of said second IGFET to said second output includes the conduction path of an eighth IGFET.

3. The combination as claimed in claim 2, further including a ninth IGFET having its conduction path connected between the first output and the drain of the second IGFET;

and

means for applying complementary signals to the control electrodes of said eighth and ninth IGFETs and a fixed potential to the control electrode of said seventh IGFET.

4. The combination comprising:

first and second power terminals for the application therebetween of an operating potential;

first and second inputs for the application thereto of complementary input signals;

first and second outputs at which are produced complementary output signals in response to said input signals;

first through sixth insulated-gate-field-effect transistors (IGFETs) of one conductivity type and seventh and eighth IGFETs of complementary conductivity type;

each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode for controlling the conductivity of the path;

means connecting the drain of the first IGFET to said first output, the drain of the second IGFET to said second output, and the sources of said first and second IGFETS in common to the drain of the third IGFET;

means connecting the drain of the fourth IGFET to said first output and the drain of the fifth IGFET to said second output and the sources of said fourth and fifth IGFETS in common to the drain of the sixth IGFET;

means connecting the control electrode of said fourth IGFET to the drain of said fifth IGFET and the control electrode of said fifth IGFET to the drain of said fourth IGFET;

means connecting the control electrodes of said first and second IGFETs to said first and second inputs, respectively;

means connecting the sources of said third and sixth IGFETs via negligible impedance means to said first power terminal;

means for applying control signals to the control electrodes of said third and sixth IGFETS for turning only one of them on at a time; and

means connecting the conduction path of said seventh IGFET between said first output and said second power terminal and the conduction path of said eighth IGFET between said second output and said second power terminal.

5. The combination as claimed in claim 4, wherein the means connecting the conduction path of said first IGFET to said first output include the conduction path of a ninth IGFET;

and wherein the means connecting the conduction path of said second IGFET to said second output includes the conduction path of a tenth IGFET.

6. The combination as claimed in claim 5, further including an eleventh IGFET having its conduction path connected between the first output and the drain of the second IGFET;

and

means for applying complementary signals to the control electrodes of said tenth and eleventh IGFETs and a fixed potential to the control electrode of said ninth IGFET.

7. The combination comprising:

first and second stages, each stage having first and second inputs and first and second outputs;

means connecting the first output of the first stage to the first input of the second stage, and the second output of the first stage to the second input of the second stage;

each one of said first and second stages including;

(a) first, second, third, fourth, fifth and sixth insulated gate field effect transistors (IGFETs);

each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode for controlling the conductivity of the path;

(b) means connecting the drain of said first IGFET to said first output and the drain of said second IGFET to said second output and the sources of said first and second IGFETs to the drain of said third IGFET;

(c) means connecting the drain of said fourth IGFET to said first output, and the drain of said fifth IGFET to said second output, and the sources of said fourth and fifth IGFETs to the drain of said sixth IGFET;

(d) means connecting the control electrodes of said first and second IGFETs to said first and second inputs, respectively;

(e) means connecting the sources of said third and sixth IGFETs via negligible impedance means to a point of fixed operating potential; and

means for applying control signals to the control electrodes of said third and sixth IGFETs for turning only one of them on at a time;

said means also including means for turning-on together the third IGFET of the first stage and the sixth IGFET of the second stage and for turning-on together the sixth IGFET of the first stage and the third IGFET of the second stage.

8. The combination as claimed in claim 7, wherein the means connecting the conduction path of said first IGFET of said first stage to said first output includes the conduction path of a ninth IGFET;

and wherein the means connecting the conduction path of said second IGFET of said first stage to said second output includes the conduction path of a tenth IGFET.

9. The combination as claimed in claim 8, further including an eleventh IGFET having its conduction path connected between the first output and the drain of said second IGFET of said first stage.

10. The combination comprising:

first and second input terminals and first and second output terminals;

first, second, third, fourth, fifth and sixth IGFETs, each one of said IGFETs having a source and a drain defining the ends of a conduction path and a control electrode;

means connecting the conduction path of said first IGFET between said first output terminal and a first node and the conduction path of said second IGFET between said second output terminal and said first node;

means connecting the conduction path of said third IGFET between said first node and a first power terminal;

means connecting the control electrode of said first IGFET to said first input terminal and the control electrode of said second IGFET to said second input terminal;

means connecting the conduction path of said fourth IGFET between said first output terminal and a second node and the conduction path of said fifth IGFET betwen said second output terminal and said second node;

means connecting the conduction path of said sixth transistor between said second node and said first power terminal;

means connecting the control electrode of said fourth IGFET to said second output terminal and the control electrode of said fifth IGFET to said first output terminal; and

means for applying signals to the control electrodes of said third and sixth IGFETs for turning-on said third IGFET and turning-off said sixth IGFET during one time interval, and for turning-off said third IGFET and turning-on said sixth IGFET during a subsequent time interval.

11. The combination comprising:

an input differential stage having first and second inputs and first and second outputs and a control terminal for the application thereto of a control signal which, when of one value, enables the differential stage whereby the signals produced at the outputs are responsive to the signals applied to the inputs and which, when of another value, disables the differential stage;

a cross-coupled differential stage having first and second input/output terminals, the first and second input/output terminals being connected respectively to the first and second outputs of the input differential stage; and

said cross-coupled differential stage having a control terminal for the application thereto of a control signal, said control signal for enabling said cross-coupled differential stage and storing the signals at said first and second outputs when said input differential stage is disabled; and

wherein said input differential stage includes three insulated gate field effect transistors (IGFETs) of one conductivity type, wherein said cross-coupled differential stage includes three IGFETs of the same one conductivity type, and wherein IGFETs of complementary conductivity type supply currents to said first and second outputs.