Architecture and process for integrating DMD with control circuit substrates

• US 5,216,537 A
• Filed: 01/02/1992
• Issued: 06/01/1993
• Est. Priority Date: 06/29/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hornbeck, Larry J.
• Primary Examiner(s): Arnold, Bruce Y.
• Assistant Examiner(s): Lester, Evelyn A.
• Application Number:
  US07/815,991
• Time in Patent Office: 516 Days
• Field of Search: 437/56, 437/61, 437/64, 437/228, 359/291, 359/295
• US Class Current: 438/23
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: Y02P 80/30 Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Claims

1. A method of forming a spatial light modulator comprising:

a. forming a first spacer layer over a substrate;

b. patterning said first spacer layer;

c. forming at least one electrode support post at a location where said first spacer layer has been patterned;

d. forming at least one electrode over said first spacer layer and said electrode support post;

e. forming a second spacer layer over said electrode;

f. patterning said second spacer layer;

g. forming at least one beam support post at a location where said second spacer layer has been patterned;

h. forming at least one electrostatically deflectable element, each having a beam and at least one hinge, over said second spacer layer and said beam support post; and

i. removing said first and second spacer layers.

2. The method of claim 1, wherein said substrate contains address circuitry.

3. The method of claim 1, wherein said substrate is a CMOS substrate.

4. The method of claim 1, wherein said electrostatically deflectable element is deflected by a voltage applied to said electrode.

5. The method of claim 1, wherein air gaps are formed between portions of said substrate and said electrode and between portions of said electrode and said electrostatically deflectable element when said first and second spacer layers are removed.

6. The method of claim 1, wherein said spatial light modulator is a DMD.

7. The method of claim 1, wherein said electrode support post and said electrode are formed essentially simultaneously.

8. The method of claim 1, wherein said electrode support post is formed from metal.

9. The method of claim 1, wherein said electrode is formed from metal.

10. The method of claim 1, wherein said beam support post and said electrostatically deflectable element are formed essentially simultaneously.