Line disturbance monitor and recorder system

• US 5,216,621 A
• Filed: 02/28/1991
• Issued: 06/01/1993
• Est. Priority Date: 02/28/1991
• Status: Expired due to Term

• Current Assignee: Mehta Tech, Inc.
• Original Assignee: Mehta Tech, Inc.
• Inventors: Dickens, Richard T.
• Primary Examiner(s): Teska, Kevin J.
• Application Number:
  US07/662,238
• Time in Patent Office: 824 Days
• Field of Search: 364/481, 364/483, 364/492, 364/482, 324/86, 235/156, 361/76, 361/80, 307/87, 322/19, 395/425, 395/600
• US Class Current: 702/58
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: G01R 31/58 Testing of lines, cables or conductors testing of electric windings G01R31/72

Abstract

A fault detection system for monitoring at least one operating parameter of an AC power transmission line includes current and/or voltage transducers connected to the transmission line for providing an analog signal representative of at least one time varying parameter of the AC power transmission. An analog-to-digital (A/D) converter samples the analog signal and produces digital sample words representing the signal. The digital sample words are provided by a data bus to a high speed DSP module which includes a number of fault trigger components for operating on the digital sample words to detect a disturbance. The DSP module generates a trigger signal when a disturbance is detected by one of the fault trigger components. The digital sample words are also provided to a DMA component, resident within a host CPU, which implements a memory allocation protocol to sequentially address a plurality of memory zones in a loop for sequential storage of the digital sample words in the discrete storage locations of the addressed memory zone. According to a fault condition memory allocation protocol, the DMA component removes at least one of the plurality of memory zones from the loop addressable by the DMA in response to receipt of a trigger signal. The removed memory zones include storage locations containing user-determined amounts of pre-fault, fault and post-fault digital sample words to fully define the AC abnormality. The DMA component continues to sequentially address the remaining ones of the plurality of memory zones as new digital sample words are received. Buffer memory zones are added to the sequential address loop for storage of the new digital sample words.

Claims

1. A fault detection system for monitoring at least one operating parameter of an AC power transmission line, comprising:

input means connectable to the transmission line for providing at least one analog signal representative of a time varying value of the at least one operating parameter;

an analog-to-digital (A/D) converter connected to said input means for sampling said at least one analog signal and producing digital sample words representing the signal;

trigger means connected to receive said digital sample words from said A/D converter for operating on said digital sample words to detect a disturbance in the at least one operating parameter and for generating a trigger signal when a disturbance is detected; and

storage means for storing said digital sample words received from said A/D converter, said storage means including;

a plurality of memory zones for storing newly acquired data in storage locations within each memory zone;

memory pointer means for sequentially addressing said plurality of memory zones in a loop for sequential storage of said digital sample words in said storage locations of the addressed memory zone; and

control means, connected to said trigger means, for removing at least one of said plurality of memory zones from said loop addressable by said memory pointer means, in response to receipt of said trigger signal;

wherein said memory pointer means continues to sequentially address the remaining ones of said plurality of memory zones in said loop as new digital sample words are received by said storage means.

2. The fault detection system of claim 1, wherein said trigger means includes:

means for generating phasor quantities representing the at least one operating parameter at the reception of said digital sample words; and

means operating on said phasor quantities to detect deviations of said phasor quantities corresponding to said disturbance.

3. The fault detection system of claim 1, wherein said control means includes means for adding a new memory zone to said loop after said at least one of said plurality of memory zones has been removed in response to receipt of said trigger signal.

4. The fault detection system of claim 1, wherein said control means includes means for maintaining said memory pointer at said least one of said plurality of memory zones to receive a number of additional digital sample words after receipt of the last trigger signal from said trigger means, said number being determined by user-entered parameters.

5. The fault detection system of claim 1, wherein said control means further includes:

means for defining at least one memory zone corresponding to pre-disturbance sample words to be removed from said loop addressable by said memory pointer means.

6. The fault detection system of claim 1, wherein said control means further includes:

means for defining at least one memory zone corresponding to post-disturbance sample words to be removed from said loop addressable by said memory pointer means.

7. The fault detection system of claim 1, further comprising a CPU having an internal permanent memory, wherein said storage means is resident within said CPU and said plurality of memory zones are within said internal permanent memory.

8. The fault detection system of claim 1, wherein said trigger means is implemented in a high speed digital signal processor (DSP).

9. A method for fault detection and monitoring of at least one operating parameter of an AC power transmission line, comprising:

generating at least one analog signal representative of a time varying value of the at least one operating parameter;

converting the analog signal to digital sample words representing the signal;

providing the digital sample words simultaneously to a trigger processor means and to data storage means by way of a data bus;

operating on the digital sample words to detect a disturbance in the at least one operating parameter and for generating a trigger signal when a disturbance is detected;

storing the digital sample words into a plurality of memory zones in the data storage means according to a memory allocation protocol by which the plurality of memory zones are sequentially addressed in a loop for sequential storage of the digital sample words in the addressed memory zone;

removing at least one of the plurality of memory zones from the loop addressable by the data storage means, in response to receipt of a trigger signal, the at least one of the memory zones containing disturbance data; and

thereafter storing newly acquired data words in the remaining ones of the plurality of memory zones sequentially addressed in a loop.

10. The method according to claim 9, further comprising the step of:

adding at least one new memory zone to the sequential memory loop in response to receipt of a trigger signal for sequential storage of new digital sample words.

11. The method according to claim 9, further comprising the step of:

receiving user input to identify the number of pre-fault or post-fault data words to be removed from the memory allocation loop in response to the receipt of the trigger signal; and

in the removing step, removing only memory zones containing data words identified by the user input.