Output ESD protection circuit

• US 5,218,222 A
• Filed: 09/16/1992
• Issued: 06/08/1993
• Est. Priority Date: 09/16/1992
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Semiconductor, Inc. (Micron Technology, Inc.)
• Inventors: Roberts, Gregory N.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US07/946,196
• Time in Patent Office: 265 Days
• Field of Search: 257/355-363
• US Class Current: 257/362
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

The basic component of the output ESD protection circuit of the present invention comprises a low resistance connected in series between an output pad and conventional active output pad pullup and pulldown drivers. In a preferred embodiment, a polysilicon resistor is connected in series between an output pad and a metal bus. On the metal bus, a lateral bipolar device is connected in parallel to an n-channel pulldown at an output node and a common potential (conventionally labeled as V_SS). The pullup device is also an active n-channel pullup device connected between an operating potential (conventionally labeled as V_CC) and the output node. Both drains of the two n-channel devices have n-well underneath the n+ diffusion in the area where metal contacts are formed to thereby prevent metal spiking to the substrate during an ESD event. This circuitry combination provides ESD protection equal to or greater than the voltage range of +8000/-2000 V for the HBM response (the Mil. Std. human body model [HBM] test model) as well as protection equal to or greater than the voltage range of +900/-700 V for the MM EIAJ response (the EIAJ machine model [MM] test model). The concept of using a low resistance between a pad and associated active devices (i.e., ESD protection circuitry) will work in combination with other ESD protection circuitry layouts and work equally well for input pad ESD protection.

Claims

1. An electrostatic discharge (ESD) protection structure for a semiconductor device constructed on a substrate comprising:

a series resistance connecting between a conductive pad and a conductive bus;

a lateral n-p-n transistor ESD protection circuit electrically connected to said conductive bus; and

an ESD output protection structure comprising active n-channel pullup and pulldown output devices connected between a first and second potential, respectively, with their outputs connected to said conductive bus.

2. The electrostatic discharge (ESD) protection structure of claim 1 wherein said substrate comprises a silicon substrate.

3. The electrostatic discharge (ESD) protection structure of claim 1 wherein said series resistance has a value of approximately 5Ω

.

4. The electrostatic discharge (ESD) protection structure of claim 1 wherein said series resistance comprises a polysilicon resistor.

5. The electrostatic discharge (ESD) protection structure of claim 1 wherein said series resistance comprises a silicided polysilicon resistor.

6. The electrostatic discharge (ESD) protection structure of claim 1 wherein said conductive pad and said conductive bus comprise metal.

7. An electrostatic discharge (ESD) output protection circuit for a dynamic random access memory semiconductor device constructed on a silicon substrate comprising:

a series silicided polysilicon resistance connecting between a conductive output pad and a conductive bus;

a lateral n-p-n transistor ESD protection circuit electrically connected to said conductive bus; and

active n-channel pullup and pulldown output devices connected between a first and second potential, respectively, with their outputs connected to said conductive bus.

8. The electrostatic discharge (ESD) protection structure of claim 7 wherein said series resistance has a value of approximately 5Ω

.

9. The electrostatic discharge (ESD) protection structure of claim 7 wherein said conductive pad and said conductive bus comprise metal.

10. An electrostatic discharge (ESD) protection structure constructed on a substrate comprising:

a series resistance connecting between a conductive pad and a conductive bus;

a lateral n-p-n transistor ESD protection circuit electrically connected to said conductive bus; and

an ESD output protection structure comprising active n-channel pullup and pulldown output devices connected between a first and second potential, respectively, with their outputs connected to said conductive bus.

11. The electrostatic discharge (ESD) protection structure of claim 10 wherein said substrate comprises a silicon substrate.

12. The electrostatic discharge (ESD) protection structure of claim 10 wherein said series resistance has a value of approximately 5Ω

.

13. The electrostatic discharge (ESD) protection structure of claim 10 wherein said series resistance comprises a polysilicon resistor.

14. The electrostatic discharge (ESD) protection structure of claim 10 wherein said series resistance comprises a silicided polysilicon resistor.

15. The electrostatic discharge (ESD) protection structure of claim 10 wherein said conductive pad and said conductive bus comprise metal.

16. An electrostatic discharge (ESD) output protection circuit constructed on a silicon substrate comprising:

a series silicided polysilicon resistance connecting between a conductive output pad and a conductive bus;

a lateral n-p-n transistor ESD protection circuit electrically connected to said conducive bus; and

active n-channel pullup and pulldown output devices connected between a first and second potential, respectively, with their outputs connected to said conductive bus.

17. The electrostatic discharge (ESD) protection structure of claim 16 wherein said series resistance has a value of approximately 5Ω

.

18. The electrostatic discharge (ESD) protection structure of claim 16 wherein said conductive pad and said conductive bus comprise metal.