Inset die lead frame configuration lead frame for a semiconductor device having means for improved busing and die-lead frame attachment

• US 5,218,229 A
• Filed: 08/30/1991
• Issued: 06/08/1993
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/753,291
• Time in Patent Office: 648 Days
• Field of Search: 357/70, 357/68, 257/666, 257/668, 257/676
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A lead frame design having a ring which encircles the die is described which provides a bus to the semiconductor die attached thereto. The bus would be most commonly used for power or ground, although other embodiments are possible. It is known that large buses designed around the periphery of a semiconductor die can cause the corners of the die to crack, causing a variety of problems including in-circuit failures, as well as using die surface area. The invention removes the need for having a large bus on the chip and places it as an element of the lead frame. A first inventive embodiment employs tape to secure the die to the lead frame, while in a second embodiment attachment of the die to the lead frame is accomplished with no glue, tape, or eutectic means, and instead uses friction between the die and flexible support pins which extend from the ring encircling the die.

Claims

1. A semiconductor device having a lead frame for the passage of an electrical potential between a semiconductor die and a host into which the semiconductor device is installed, the die having first and second parallel major surfaces, and the lead frame comprising:

a) first and second parallel major surfaces;

b) lead fingers electrically coupled with said die;

c) leads electrically coupled to said lead fingers, said leads allowing for electrical coupling with the host into which the semiconductor device is installed;

d) a lead frame portion having a void therein for receiving the die such that said first major surface of said die is positioned inferiorly to said first major surface of said lead frame and said second major surface of said die is positioned superiorly to said second major surface of said lead frame wherein said lead frame portion is interposed between said die and said lead fingers.

2. The semiconductor device of claim 1 wherein said die is attached to said lead frame by tape which contacts said first major surface of said die and said second major surface of said lead frame.

3. The semiconductor device of claim 2 wherein said tape comprises a plastic sheet coated on one side by a layer of thermoplastic, said thermoplastic contacting said first major surface of said die and said second major surface of said lead frame.

4. The semiconductor device of claim 1 wherein said die is attached to said lead frame by a plurality of support pins protruding from said lead frame portion having said void, said support pins applying lateral pressure to said die.

5. The semiconductor device of claim 1 wherein said die comprises bond pads which are electrically coupled to said lead fingers by bond wires.

6. The semiconductor device of claim 1 wherein said lead frame portion having said void is electrically coupled to one of said leads, and wherein said die is electrically coupled to said lead frame portion.

7. The semiconductor device of claim 1 wherein said lead frame portion having said void comprises a first segment which is electrically isolated from a second segment of said lead frame portion.

8. The semiconductor device of claim 6 wherein said lead frame portion having said void comprises a first segment which is electrically isolated from a second segment of said lead frame portion, and wherein said first and second segments are electrically coupled to a different lead, and wherein said die is electrically coupled to said segments.

9. A lead frame for the passage of an electrical potential between a semiconductor die and a host into which the semiconductor device is installed, the die having first and second parallel major surfaces, and the lead frame comprising:

a) first and second parallel major surfaces;

b) lead fingers electrically coupled with said die;

c) leads electrically coupled to said lead fingers, said leads allowing for electrical coupling with the host into which the semiconductor device is installed;

d) a lead frame portion having a void therein for receiving the die such that said first major surface of said die is positioned inferiorly to said first major surface of said lead frame and said second major surface of said die is positioned superiorly to said second major surface of said lead frame wherein said lead frame portion is interposed between said die and said lead fingers.

10. The lead frame of claim 9 wherein said die is attached to said lead frame by tape which contacts said first major surface of said die and said second major surface of said lead frame.

11. The lead frame of claim 10 wherein said tape comprises a plastic sheet coated on one side by a layer of thermoplastic, said thermoplastic contacting said first major surface of said die and said second major surface of said lead frame.

12. The lead frame of claim 9 wherein said die is attached to said lead frame by a plurality of support pins protruding from said lead frame portion having said void, said support pins applying lateral pressure to said die.

13. The lead frame of claim 9 wherein said die comprises bond pads which are electrically coupled to said lead fingers by bond wires.

14. The lead frame of claim 9 wherein said lead frame portion having said void is electrically coupled to one of said leads, and wherein said die is electrically coupled to said lead frame portion.

15. The lead frame of claim 9 wherein said lead frame portion having said void comprises a first segment which is electrically isolated from a second segment of said lead frame portion.

16. The lead frame of claim 14 wherein said lead frame portion having said void comprises a first segment which is electrically isolated from a second segment of said lead frame portion, and wherein said first and second segments are electrically coupled to a different lead, and wherein said die is electrically coupled to said segments.

17. A lead frame for the passage of an electrical potential between a semiconductor die and a host into which the semiconductor die is installed, the die having first and second parallel major surfaces, the lead frame comprising:

a) first and second parallel major surfaces;

b) lead fingers electrically coupled with said die;

c) leads electrically coupled to said lead fingers, said leads allowing for electrical coupling with the host into which the semiconductor device is installed;

d) a lead frame portion having a void therein for receiving the die, the lead frame having a ring which encircles the die thereby providing a bus to the die when the die is attached to the lead frame, said first major surface of said die being positioned inferiorly to said first major surface of said lead frame and said second major surface of said die being positioned superiorly to said second major surface of said lead frame wherein said ring is interposed between said die and said lead fingers.